An Intro to Level-Sensitive Interrupts

The later versions of the PCI spec permit device adapters to share the same IRQ signal line. The shareable IRQ signal lines are typically asserted when driven low and have a pull-up resistor on the system board that maintains the signal in the deasserted state when no devices are requesting service. An interrupt request is placed on the signal line by driving the signal low and the interrupt controller input (on the IO APIC) is programmed to recognize a static electrical low as a valid interrupt request. This is referred to as an active low, level-sensitive interrupt request. The interrupt controller (the IO APIC) sets the IRR bit associated with that input and forwards the request to the processor for servicing. Unlike the edge-triggered interrupt, however, the interrupt controller does not clear the IRR bit after forwarding the request to the processor for servicing. If it were to do so, the controller would immediately recognize the same request from the same device again (because the device hasn't been serviced yet and it is therefore still driving the line low).

The IRR bit remains set to one, inhibiting the recognition of another request until the IRR bit is cleared. The processor executes the body of the device adapter's interrupt handler. The handler interacts with the device to service its request, and the act of servicing the request causes the device to cease driving the signal line low. Multiple device's can share the line and can drive it low simultaneously. This being the case, when the first device that is driving the line low has been serviced and ceases driving the line low, the line would remain low because the other devices that are driving it low have not yet been serviced.

At the end of the first device adapter's interrupt handler, the handler writes to the interrupt controller's (the IO APIC's) End-of-Interrupt (EOI) register, causing the controller to clear the IRR bit associated with that input. The controller will then recognize a request on that input when the line becomes low again (or if it is already low).

Additional information on shareable interrupts can be found in “The EOI Register” on page 1578.