Performance Monitoring

The Pentium® was the first IA32 processor to implement logic to log performance measurement information. All subsequent IA32 processors implement Performance Monitoring logic (but the Pentium®, P6 and Pentium® 4 implementations are not compatible with each other).

The Pentium®'s Performance Monitoring logic consisted of the following (see Figure 21-12 on page 506):

• Two 40-bit performance counters implemented as MSRs (PerfCtr0 and PerfCtr1).

• The 32-bit CESR (Counter Event Select Register) implemented as an MSR. This register was divided into two sets of bit fields (one set for each of the two counters):

  - The 6-bit CESR[ES] (Event Select) field selected the event type to be measured. The event types are defined in Appendix B of the IA32 Intel® Architecture Software Developer's Manual Volume 3: System Programming Guide.

  - The 3-bit CESR[CC] (Counter Control) field:

  - 000b and 100b: Count nothing (counter disabled).
  
  

  - 001b: Count the selected event when the CPL = 0, 1, or 2.
  
  

  - 010b: Count the selected event when the CPL = 3.
  
  

  - 011b: Count the selected event regardless of the CPL.
  
  

  - 101b: Count clocks (i.e., the duration of the event) when the CPL = 0, 1, or 2.
  
  

  - 110b: Count clocks (i.e., the duration of the event) while the CPL = 3.
  
  

  - 111b: Count clocks (i.e., the duration of the event) regardless of the CPL.
  
  

  - CESR[PC] (Pin Control) bit:

  - 1 = The processor asserted the PM output pin associated with the respective counter when that counter overflowed.

  - 0 = The processor asserted the PM output pin associated with the respective counter each time that the counter was incremented.

Figure 21-12. Pentium® Performance Monitoring Register Set

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