The FSB and BSB

Refer to Figure 26-7 on page 670.

The FSB Protocol

The Pentium® II used the same FSB protocol as the Pentium® Pro.

The Processor Core and Bus Frequencies

The Pentium® II processor was available with core speeds from 233 to 450MHz. The system board logic provided the BCLK to the cartridge as well as to all other agents that resided on the FSB. On the cartridge, the BCLK was supplied to the processor core's PLL (Phase Locked Loop) and multiplied to develop the core's internal clock as well as the clock for the L2 Cache bus (i.e., the BSB).

As with the Pentium® Pro processor (see chapter 3 of the MindShare book entitled Pentium® Pro and Pentium® II System Architecture, Second Edition), the Pentium® II processor sampled its LINT[1:0], A20M#, and IGNNE# inputs during RESET#'s assertion period to determine the processor core clock frequency. The PLL multiplied the BCLK frequency by the factor delivered on these four inputs to produce the core clock frequency. At the trailing-edge (i.e., the deassertion) of RESET#, the value on these four pins was latched and used throughout the entire power-up session by the PLL to maintain the selected core clock speed.

On all Pentium® II processors, the L2 Cache bus (i.e., the BSB) operated at 50% of the core frequency. As an example, a 266MHz Pentium® II processor's PLL multiplied the 66MHz BCLK by four to yield the core frequency. This yielded a BSB frequency of 133MHz. The later versions of the processor supported up to a 100MHz BCLK and processor core speeds of up to 450MHz.

The FSB Arbitration Scheme

The Pentium® Pro Processor FSB Arbitration

The Pentium® Pro bus supported up to four processors in a rotational priority scheme (see “Symmetric Agent Arbitration—Democracy at Work” on page 216 on the CD). Each processor had four processor bus request pins designated as BR[3:0]#. These four pins were connected to the bus request traces (BREQ[3:0]#) on the system board as illustrated in Figure 26-11 on page 677. A complete description of the processor bus arbitration can be found in the section entitled “Pentium® 4 CPU Arbitration” on page 1149.

Pentium® II Processor FSB Arbitration

The Pentium® II processor's FSB arbitration scheme was identical to that of the Pentium® Pro processor, but it only supported up to two processors in a rotation. The processor only had two processor bus request pins, BR[1:0]# interconnected as illustrated in Figure 26-12 on page 678.

The number of processors a Xeon supports on the FSB depends on the version of the Xeon:

• An MP (Multiprocessor) version of the Xeon supports a rotation of four processors on the FSB and each of those processors has four Bus Request pins (BR[3:0]#) interconnected as shown in Figure 26-11 on page 677.

• A DP (Dual Processor) version of the Xeon supports a rotation of two processors on the FSB and each of those processors has four Bus Request pins (BR[3:0]#) interconnected as shown in Figure 26-12 on page 678.

The BSB and the L2 Cache

The BSB Frequency

As described earlier, the BSB on all of the Pentium® II processor versions operated at 50% of the processor core's operational frequency.

The L2 Cache

All versions of the Pentium® II processor had a 512KB L2 Cache. It used a proprietary Intel®-designed tag SRAM (the Tag SRAM is the directory for the four banks of data SRAM that comprise the L2 Cache) designated as the 82459AB. Intel® did not define the architecture of the L2 Cache (i.e., the set-associativity), but that was easily determined using the CPUID instruction.