Introduction

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Introduction

The initial steps in the system startup are as follows:

1.	The power is off.
2.	When the power is turned on, the power supply keeps the PowerGood signal deasserted to the chipset until the supply voltages are up and stable. During this period of time, the chipset keeps reset asserted to the processor(s) and to all other devices until the power is stable and for a period of time afterwards (to allow sufficient time for clock generators to spin up, etc.).
3.	While reset is still asserted to the processors, the chipset (specifically, the Root Complex, MCH, or North Bridge) drives the contents of its processor configuration register onto the FSB signal lines that provide startup configuration information to the processors (see “Pentium® 4 PowerOn Configuration” on page 855).
4.	The chipset then deasserts the reset signal to the processors and the processors latch the configuration signals on the trailing-edge of reset.
5.	The effects that reset's assertion has on the processor(s) is covered in “The Processor's State After Reset” on page 877.
6.	If the configuration information instructed the processors to execute the BIST, the BIST runs to completion before the processor starts normal operation. The duration of the BIST is processor design-specific. During the BIST execution, the processor cannot monitor transactions initiated by other FSB agents. For this reason, the processor will continually toggle the Block Next Request (BNR#) signal for the duration of the BIST. This prevents any other FSB agent from initiating a transaction until the BIST has been completed.
7.	Before any of the processors start fetching instructions from memory, the processor that is going to perform the initial system startup and the OS boot (it is referred to as the Boot Strap Processor, or BSP) must be selected. The processors perform transactions on the FSB to decide which will be the BSP. The other processors are referred to as Application Processors, or APs and they remain in the halt state (drawing a minimum of power) until they are instructed to execute a program by the program executing on the BSP.
8.	At this point, the BSP starts fetching instructions from memory at the power-on restart address (FFFFFFF0h). This program is fetched from the Boot ROM (also called the system BIOS ROM).
9.	The BIOS startup code accomplishes the following: - It executes the Power-On Self-Test (POST) code to test the processor's basic functionality as well as the basic functionality of the system board components and device adapters that will be necessary to boot the OS into memory. - It configures the processor in preparation for booting the OS into memory. - It creates an entry in the Multiprocessing Table and in the ACPI Table indicating the BSP's type and capabilities. - It places a program in memory to be executed by each of the APs (which are currently in the halt state). - It instructs its Local APIC to send a Startup IPI (Inter Processor Interrupt; SIPI) to all of the other Local APICs in the system. - Upon receipt of the SIPI, each of the APs, in turn, executes the program they have been instructed to execute. The execution of this program causes the AP to be configured and causes it to make an entry in the Multiprocessing Table and in the ACPI Table indicating the AP's type and capabilities. At the end of the startup program, the AP halts.
10.	The program executing on the BSP then reads the OS startup code into memory and causes the processor to execute it.
11.	The OS startup program boots the remainder of the OS kernel into memory, sets up any data structures necessary for the OS's use (the GDT, the LDTs, Page Directories, Page Tables, etc.). The OS loads all of the loadable device drivers associated with the device adapters installed in the system. The OS also finishes the configuration of the device adapters throughout the system.
12.	That's it! The system is ready for normal operation.

The sections in this chapter describe many of the steps just introduced.

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Table of Contents for Introduction

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Introduction

Table of Contents for
Introduction