Enabling/Disabling the Caches
by Bob Colwell, Tom Shanley
The Unabridged Pentium 4 IA32 Processor Genealogy
- Copyright
- At-a-Glance Table of Contents
- Figures
- Tables
- Acknowledgments
- About This Book
- Introduction
- Single-/MultiTask OS Background
- The 386
- 386 Real Mode Operation
- Protected Mode Introduction
- Intro to Segmentation in Protected Mode
- Code Segments
- Data and Stack Segments
- Creating a Task
- Mechanics of a Task Switch
- 386 Demand Mode Paging
- Problem—Loading Entire Task into Memory is Wasteful
- Solution—Load Part and Keep Remainder on Disk
- Problem—Running Two (or more) DOS Programs
- Solution—Redirect Memory Accesses to Separate Memory Areas
- Global Solution—Map Linear Address to Disk Address or to a Different Physical Memory Address
- The Paging Unit Is the Translator
- Three Possible Page Lookup Methods
- IA32 Page Lookup Method
- Enabling Paging
- Page Directory and Page Tables
- Finding the Location of a Physical Page
- Eliminating the Directory Lookup
- Checking Page Access Permission
- Page Faults
- Usage of the Dirty and Accessed Bits
- Demand Mode Paging Evolution
- The Flat Model
- Interrupts and Exceptions
- Special Note
- General
- Hardware Interrupts
- Software-Generated Exceptions
- Interrupt/Exception Priority
- Real Mode Interrupt/Exception Handling
- Protected Mode Interrupt/Exception Handling
- Interrupt/Exception Handling in VM86 Mode
- Exception Error Codes
- The Resume Flag Prevents Multiple Debug Exceptions
- Special Case—Interrupts Disabled While Updating SS:ESP
- Detailed Description of the Software Exceptions
- Virtual 8086 Mode
- A Special Note
- DOS Application—Portrait of an Anarchist
- Solution—Set a Watchdog on the DOS Application
- The Virtual Machine Monitor (VMM)
- Entering or Reentering VM86 Mode
- An Interrupt or Exception Causes an Exit From VM86 Mode
- A Task Switch Causes an EFlags Update
- DOS Task's Memory Usage
- The Privilege Level of a VM86 Task
- Restricting IO Accesses
- IOPL-Sensitive Instructions
- Interrupt/Exception Generation and Handling
- Registers Accessible in Real/VM86 Mode
- Instructions Usable in Real/VM86 Mode
- VM86 Mode Evolution
- The Debug Registers
- 486
- Pentium®
- Intro to the P6 Core and FSB
- Pentium® Pro Software Enhancements
- Pentium® Pro Software Enhancements
- MicroCode Update Feature
- The Problem
- The Solution
- The Microcode Update Image
- Matching the Image to a Processor
- The Microcode Update Loader
- Updates in a Multiprocessor System
- The Image Management BIOS
- When Must the Image Upload Take Place?
- Determining if a New Update Supersedes a Previously-Loaded Update
- Effect of RESET# Or INIT# on a Previously-Loaded Update
- Pentium® II
- Pentium® II Hardware Overview
- The Pentium® Pro and Pentium® II: Same CPU, Different Package
- Dual-Independent Bus Architecture (DIBA)
- IOQ Depth
- Pentium® Pro/Pentium® II Differences
- One Product Yields Three Product Lines
- The Pentium® II/Xeon/Celeron Roadmap
- The Cartridge
- The Core
- The FSB and BSB
- The Introduction of the Celeron
- Miscellaneous Hardware Stuff
- Pentium® II Power Management Features
- Pentium® II Software Enhancements
- Pentium® II Xeon Features
- Pentium® II Hardware Overview
- Pentium® III
- Pentium® 4
- Pentium® 4 Road Map
- Pentium® 4 System Overview
- Pentium® 4 Processor Overview
- The Pentium® 4 Processor Family
- Pentium® III/Pentium® 4 Differences
- Pentium® 4/Pentium® 4 Prescott Differences
- Pentium® 4 Processor Basic Organization
- The FSB is Tuned for Multiprocessing
- Intro to the FSB Enhancements
- IA Instructions Vary in Length and Are Complex
- The Trace Cache
- There Are Two Pipeline Sections
- The μop Pipeline
- The IA32 Data Register Set Was Small
- Speculative Execution
- Pentium® 4 PowerOn Configuration
- Configuration on Trailing-Edge of Reset
- Setup and Hold Time Requirements
- Built-In Self-Test (BIST) Trigger
- Assignment of IDs to the Processor
- Error Observation Options
- In-Order Queue Depth Selection
- Power-On Restart Address
- Tri-State Mode
- Processor Core Speed Selection
- Bus Parking Option
- Hyper-Threading Option
- Program-Accessible Startup Features
- Pentium® 4 Processor Startup
- Pentium® 4 Core Description
- Hyper-Threading
- General
- Background
- The HT Approach
- Overview of HT Resource Usage
- HT and the Data TLB
- HT and the FSB
- The IOQ Depth Was Increased
- HT Performance Issues
- HT and Serializing Instructions
- HT and the Microcode Update Feature
- HT Cache-Related Issues
- HT and the TLBs
- HT and the Thermal Monitor Feature
- HT and External Pin Usage
- The Pentium® 4 Caches
- Pentium® 4 Handling of Loads and Stores
- The Pentium® 4 Prescott
- Introduction
- Increased Pipeline Depth
- Trace Cache Improvements
- Increased Number of WCBs
- L1 Data Cache Changes
- Increased L2 Cache Size
- Enhanced Branch Prediction
- Store Forwarding Improved
- SSE3 Instruction Set
- Increased Elimination of Dependencies
- Enhanced Shifter/Rotator
- Integer Multiply Enhanced
- Scheduler Enhancements
- Fixed the MXCSR Serialization Problem
- Data Prefetch Instruction Execution Enhanced
- Improved the Hardware Data Prefetcher
- Hyper-Threading Improved
- Pentium® 4 FSB Electrical Characteristics
- Intro to the Pentium® 4 FSB
- Pentium® 4 CPU Arbitration
- Pentium® 4 Priority Agent Arbitration
- Pentium® 4 Locked Transaction Series
- Pentium® 4 FSB Blocking
- Pentium® 4 FSB Request Phase
- Pentium® 4 FSB Snoop Phase
- Pentium® 4 FSB Response and Data Phases
- A Note on Deferred Transactions
- The Purpose of the Response Phase
- The Response Phase Signal Group
- The Response Phase Start Point
- The Response Phase End Point
- The Response Types
- The Response Phase May Complete a Transaction
- The Data Phase Signal Group
- Five Example Scenarios
- Data Phase Wait States
- The Response Phase Parity
- Data Bus Parity
- Pentium® 4 FSB Transaction Deferral
- Pentium® 4 FSB IO Transactions
- Pentium® 4 FSB Central Agent Transactions
- Pentium® 4 FSB Miscellaneous Signals
- Pentium® 4 Software Enhancements
- The Foundation
- Miscellaneous New Instructions
- Enhanced CPUID Instruction
- The SSE2 Instruction Set
- The SSE3 Instruction Set
- Local APIC Enhancements
- The Thermal Monitoring Facilities
- FPU Enhancement
- The MSRs
- The Machine Check Architecture
- Last Branch, Interrupt, and Exception Recording
- The Debug Store (DS) Mechanism
- New Exceptions
- The Performance Monitoring Facility
- Pentium® 4 Xeon Features
- Pentium® M
- Pentium® M Processor
- Background
- The Pentium® M and Centrino
- Characteristics Overview
- The FSB Characteristics
- Enhanced Power Management Characteristics
- Three Different Packaging Models
- Improved Thermal Monitor Mode
- Enhanced Branch Prediction
- μop Fusion
- Advanced Stack Management
- Miscellaneous
- The Data Cache and Hyper-Threading
- The Next Pentium® M
- Pentium® M Processor
- Additional Topics
- CPU Identification
- System Management Mode (SMM)
- What Falls Under the Heading of System Management?
- The Genesis of SMM
- SMM Has Its Own Private Memory Space
- The Basic Elements of SMM
- A Very Simple Example Scenario
- How the Processor Knows the SM Memory Start Address
- Protected Mode, Paging and PAE-36 Mode Are Disabled
- The Organization of SM RAM
- Entering SMM
- Exiting SMM
- Caching from SM Memory
- Setting Up the SMI Handler in SM Memory
- Relocating the SM RAM Base Address
- SMM in an MP System
- The Local and IO APICs
- Before the Advent of the APIC
- MP Systems Need a Better Interrupt Distribution Mechanism
- A Short History of the APIC
- Detecting the Presence and Version of the Local APIC
- Enabling/Disabling the Local APIC
- Local Cluster and APIC ID Assignment
- An Introduction to the Interrupt Sources
- Introduction to Interrupt Priority
- An Intro to Edge-Triggered Interrupts
- An Intro to Level-Sensitive Interrupts
- The Local APIC Register Set
- Locally Generated Interrupts
- Task and Processor Priority
- Interrupt Messages
- The IO APIC
- Message Signaled Interrupts (MSI)
- Message Format
- The Spurious Interrupt Vector
- The Agents in an Interrupt Message Transaction
- BSP Selection Process
- The APIC, the MPS and ACPI
- Acronyms
- CD-ROM Warranty
- Index
Enabling/Disabling the Caches
The caches are enabled or disabled using the CD and NW bits in CR0 (see Table 40-1 on page 1013).
| CR0[CD] | CR0[NW] | Description |
|---|---|---|
| 0 | 0 | Caching is fully enabled. |
| 0 | 1 | Invalid and Reserved. |
| 1 | 0 | The cache is locked. No new lines are loaded into the cache, but cache lookups are performed. |
| 1 | 1 | Caching is fully disabled. |
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