The AutoHalt Power Down State
Description
Refer to Figure 27-2 on page 688. When a HLT (Halt) instruction is executed, the processor generates a Special transaction (see “The Special Transaction” on page 1306) on the FSB to broadcast a Halt message to the system. It then leaves the Normal state and enters the AutoHalt Power Down state. This state has the following characteristics:
The processor powers down all logic except the logic that is necessary for the recognition of interrupts and the snooping of memory accesses generated by other FSB agents.
The BCLK signal on the FSB continues to run.
The processor services any snoop events (i.e., memory transactions generated by other agents on the FSB) and then returns to the AutoHalt Power Down state. To do this, the processor temporarily transitions from the AutoHalt Power Down state to the Halt/Grant Snoop state. While in this state, it presents the memory address received from the other agent to the three caches within the processor for a lookup. It then presents the snoop result to the other agent as well as to the system memory controller on the HIT# and HITM# signals. After the snoop is complete, the processor returns to the AutoHalt Power Down state.
Upon the occurrence of an interrupt event (RESET#, SMI#, BINIT#, INIT#, or LINT[1:0]—NMI or INTR), the processor exits the AutoHalt Power Down state and returns to the Normal state to service the interrupt.
Upon return from the SMI interrupt handler, the processor either enters the Normal state (if the instruction returned to is an instruction other than a HLT) or the AutoHalt Power Down state (if the instruction returned to is a HLT instruction).
If the processor's FLUSH# input is asserted while the processor is in the AutoHalt Power Down state, the flush is serviced (i.e., all modified lines are written back to system memory and the processor caches are then invalidated). Upon completion of the writeback operation, the processor re-enters the AutoHalt Power Down state.
The system board logic (specifically, the chipset) may assert the STPCLK# signal to the processor while the processor is in the AutoHalt Power Down state. This causes the processor to leave the AutoHalt Power Down state and enter the Stop Grant state. The processor remains in the Stop Grant state until STPCLK# is removed and then re-enters the AutoHalt Power Down state.
The Chipset's Response to the Halt Message
When the chipset receives the Halt message from the processor (in the Special transaction), the action(s) taken by the processor are design-specific. As an example, the chipset might be designed to power down some of the system board logic during the period of time that the processor remains inactive. It could then reapply power to that logic when the processor arbitrates for ownership of the FSB to initiate a transaction on the FSB.