HT and External Pin Usage

STPCLK# Pin

To conserve on power consumption during a period of time when the processor is not needed, the chipset can assert the STPCLK# input to the physical processor. This has the following effects on an HT-capable processor:

• When asserted, the core transitions to the Stop-Grant power conservation state (see “The Stop Grant State” on page 688). Program execution is halted but the core continues to service snoops.

• All logical processors stop program execution and none of them respond to any interrupts.

• In an MP system, this pin on all physical processors are usually tied together, so the assertion of STPCLK# affects all logical processors in the system simultaneously.

LINT0 AND LINT1 Pins

These two signals are inputs to the physical processor and are used to alert the processor to platform-specific external events. On an HT-capable processor, they have the following characteristics:

• Within the physical processor package, they are tied to the LINT0 and LINT1 inputs on all of the Local APICs (see “The Local and IO APICs” on page 1497) associated with each logical processor in the package.

• If either pin is asserted, the interrupt is detected by all of the Local APICs.

• Whether or not a Local APIC actually interrupts its logical processor depends on the state of the mask bit in that pin's LVT.

• In an MP system, these two pins are usually not used to deliver interrupts to a logical processor. Rather:

  - All interrupts from device adapters are delivered to a logical processor via a memory-mapped IO write (i.e., an interrupt message) from the IO APIC in the chipset.

  - All interrupts from other logical processors are delivered to a logical processor via IPIs.

A20M# Pin

Refer to “A20 Mask” on page 419 for a detailed description of this physical processor input.

The assertion of A20M# to the physical processor affects the operation of all logical processors within a physical processor.