The Previous Chapter
This chapter provided a detailed description of FSB Central Agent transactions. It included:
Point-to-Point vs. Broadcast.
The Interrupt Acknowledge Transaction.
The Special Transaction.
The BTM Transaction Is Used for Program Debug.
This Chapter
This chapter provides a detailed description of FSB signal that were not described in earlier chapters.
The Next Chapter
This chapter provides a detailed description of the software enhancements implemented in the Pentium® 4 processor. This includes:
Miscellaneous New Instructions.
Enhanced CPUID Instruction.
The SSE2 Instruction Set.
The SSE3 Instruction Set.
Local APIC Enhancements.
The Thermal Monitoring Facilities.
FPU Enhancement.
The MSRs.
The Machine Check Architecture.
Last Branch, Interrupt, and Exception Recording.
The Debug Store (DS) Mechanism.
New Exceptions.
The Performance Monitoring Facility.
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