SMM in an MP System

The following should be noted when designing multiple-processor systems:

• Any processor in an MP system can respond to an SMM.

• The SM RAM memory for different processors can be overlapped in the same memory space, but each processor must have its own State Save Area (see “In an MP System, Each Processor Must Have a Separate State Save Area” on page 1495) and its own dynamic data storage area. Code and static data can be shared among processors.

• At startup time the system configuration software must assign a different SM Base address for each processor (see “Relocating the SM RAM Base Address” on page 1495).

• The processors can receive SMIs through their SMI# pins or via SMI IPI messages received through the APIC interface. The APIC interface can distribute SMIs to different processors.

• Two or more processors can be executing in SMM at the same time.

• When operating Pentium® processors in dual processor (DP) mode, the SMIACT# pin had to be driven only by the MRM processor and could only be sampled with ADS#.