Determining the Processor's Cache Sizes and Structures

The OS can tune its use of memory to yield optimal processor performance if it understands the geometry of the processor's caches and TLBs. The CPUID instruction may be executed with a request type 2 to return information regarding the size and organization of:

• the L2 Cache.

• the L3 Cache (if there is one).

• the L1 Data Cache.

• the L1 Code Cache (the Trace Cache in the Pentium® 4 family).

• the Code TLB.

• the Data TLBs.

For detailed information on the CPUID instruction, refer to “CPU Identification” on page 1443.