The Contents of Request Packet A
Description
Table 49-4 on page 1213 defines the information driven onto the Request Phase signal group in Packet A. It consists of the address and transaction type. This is sufficient information for:
Response Agents to begin the decode to determine which of them is the target device.
Snoop Agents to begin the snoop in their internal caches (if it is a memory access).
| Signal(s) | Description |
|---|---|
| ADS# | Address Strobe is asserted by the agent issuing the request (the Request Agent), indicating that the agent is providing all of the request information in two packets. This information represents the address, the request type, and additional information about the transaction. |
| A[35:3]# | The qword-aligned IO or memory address (see Figure 49-5 on page 1214) is presented to the other agents. If this is a Deferred Reply transaction, the address of the Request Agent that initiated the previously-deferred transaction is presented, as well as the transaction ID. |
| REQ[4:0]# | Request. The request (i.e., transaction type) is presented on these signal lines (see Figure 49-6 on page 1215). Table 49-5 on page 1216 defines the request codes currently defined for the Pentium® 4 processor. |
Figure 49-5. Qword-Aligned Address Bus
Table 49-5 on page 1216 details the encoding of the transaction types.
32-bit vs. 36-bit Addresses
All of the memory transaction types contain an address size field (see ASZ in Table 49-5 on page 1216 and Table 49-7 on page 1217). Please note that although the spec only currently defines two ASZ bit patterns, there are two more available for future assignment. In other words, Intel® may design future processors with address buses wider (or, although unlikely, more narrow) than the current 36 bits. It is currently permissible to design:
A 32-bit address Request Agent. Request Agents that are only capable of generating 32-bit memory addresses and only use up to A[31]# (i.e., they don't drive A[35:32]#). They are therefore only capable of addressing memory that resides in the lower 4GB. Whenever a Request Agent of this type generates a memory transaction, it must indicate (on the ASZ lines) that it is only generating a 32-bit address on the lower part of the bus to address a memory target that resides below the 4GB boundary.
A 32-bit address memory Response Agent. Memory Response Agents that only latch and decode up to A[31]#. By definition, these memory Response Agents reside in the lower 4GB of memory space. A memory agent of this type must check the state of the ASZ lines received in request packet A and only decode the address if ASZ indicates that it is below the 4GB boundary. If it ignored ASZ, it may decode the lower 32 bits of a 36-bit (or wider) address destined for a memory target that resides above the 4GB - 1 boundary. This could result in two memory Response Agents driving bus signals simultaneously.
A 36-bit address Request Agent. Request Agents that are capable of generating 36-bit memory addresses and use up to A[35]#. They are therefore capable of addressing memory that resides in the lower 64GB. Whenever a Request Agent of this type generates a memory transaction, it must indicate (on the ASZ lines) whether it is generating an address above or below the 4GB boundary.
A 36-bit address memory Response Agent. Memory Response Agents that latch and decode up to A[35]#. By definition, these memory Response Agents can reside anywhere in the lower 64GB of memory space. A memory agent of this type must check the state of the ASZ lines received in request packet A and only decode the address if ASZ indicates that it is below the 4GB boundary or below the 64GB boundary. If it ignored ASZ, it may decode the lower 36 bits of an address destined for a memory target that resides above the 64GB boundary (this wouldn't happen now, but it could happen in the future). This could result in two memory Response Agents driving bus signals simultaneously.