HT and the TLBs

Refer to “Eliminating the Directory Lookup” on page 234 for a description of the TLB.

Whether a processor's TLBs are shared by the logical processors in a physical processor or they are replicated for each logical processor is implementation-specific. As of this writing (03/09/04), the DTLB is shared and the ITLBs are replicated.

When a Page Table Entry (PTE) for a 4KB page, or a Page Directory Entry (PDE) for a large page (2MB or 4MB) is cached in the TLB, it is tagged with the logical processor ID of the logical processor that caused the table lookup. If a thread executing on a logical processor should load a new value into CR3, CR4, or should execute the INVLPG instruction, only the TLB entries that are tagged for that logical processor are flushed.