The FSB Interface Unit

The Agent Types

There are three types of agents involved in a FSB transaction:

• The Request Agent issues the transaction request.

• The Response Agent is the device that acts as the target of the transaction.

• The Snoop Agents are the entities that contain caches (typically, the processors). If the transaction is a memory transaction, they perform a lookup in their caches using the transaction's address and report the snoop result (to the Request and Response Agents) in the transaction's Snoop Phase.

The Request Agent Types

There are two types of Request Agents:

• The Symmetric Request Agents are the processors. They use a symmetric (rotational) bus arbitration scheme.

• The Priority Agents are agents other than processors that perform transactions on the FSB. An example would be the North bridge, MCH, or Root Complex (in other words, the chipset).

The Transaction Phases

Each transaction performed on the FSB consists of the following phases:

• The Request Phase. The transaction request is issued.

• The Error Phase. If any FSB agents detected a parity error, they assert AERR# to the Request Agent and the transaction is aborted. This phase was eliminated with the advent of the Pentium® 4 processor.

• The Snoop Phase. The Snoop Agents report the snoop result.

• The Response Phase. The Response Agent indicates how it will treat the transaction (Retry, Deferred, Hard Failure, Supply Data, Accept Data, or Hit on Modified Line).

• The Data Phase.

The Transaction Types

The FSB interface Unit performs FSB transactions when requested to do so by the L2 Cache or the processor core. The transactions types the processor performs on the FSB are:

• IO Read or Write Transaction.

• Memory Read Transaction.

• Memory Write Transaction.

  - Memory Write. This is the regular memory write transaction that is used for most memory writes.
  
  

  - Memory Line Writeback. Used to write a modified line back to memory.
  
  

• Memory Read and Invalidate Transaction. Used to kill a line in the caches of other processors, or to read a line with the intent to modify it.

• Special Transaction. Used to broadcast a message to the platform.

• Interrupt Acknowledge Transaction. Used to obtain the interrupt vector from the interrupt controller.

• Branch Trace Message Transaction. Used as debug aid.

• Deferred Reply Transaction.