HT and the FSB

When a code or data request misses the processor caches and must be forwarded upstream to system memory, the request must be queued in the processor's FSB interface. The FSB interface treats requests issued by the two logical processors on a first-come, first-serve basis.

When a transaction is forwarded onto the FSB, the Agent ID issued in the transaction's Request Phase is the ID of the logical processor that the request is associated with. When a modified line is being pushed back to system memory to make room for a new line being read into the cache, the line write transaction uses the ID of the logical processor whose code caused the read of the new line. When a code read transaction is initiated on the FSB at the request of the Instruction Prefetcher, the transaction uses the ID of the logical processor that caused the prefetch.

The chipset (specifically, the Root Complex, MCH or North Bridge) can use the agent ID (i.e., the logical processor ID) in each processor-initiated FSB memory transaction to prioritize accesses to system memory (ensuring that each of the logical processors in each physical processor has fair access to system memory).The exact method used by the chipset to ensure fairness would be chipset design-specific.