Local APIC Enhancements

The following enhancements were made to the processor's Local APIC:

• An entry was added to the Local Vector Table (see Figure 56-10 on page 1339) for the Thermal Sensor interrupt. Refer to “The Local Vector Table” on page 1539 and “The Thermal Sensor Interrupt” on page 1548.

  Figure 56-10. The Local APIC Register Set

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• The APIC ID register was enhanced (see “The Local APIC ID” on page 864 and “APIC ID Assignment” on page 1514 for additional information). For the P6 and Pentium®, the APIC ID field is 4 bits, and encodings 0h through Eh can be used to uniquely identify 15 different processors connected to the APIC bus. For the Pentium® 4, the xAPIC spec extends the Local APIC ID field to 8 bits allowing up to 255 processors in the system.

• The 3-wire APIC bus was eliminated and interrupt messages are exchanged between the Local APICs within the processors and the IO APIC module in the chipset by performing memory-mapped IO write transactions on the FSB. Refer to “Interrupt Messages” on page 1555 and “Message Format” on page 1591 for more information.