The Response Phase Parity
General
The RS[2:0]# signals are protected by the RSP# parity bit. RSP# is driven in each BCLK cycle of the Response Phase, it must be left high or driven low to force an even number of electrical lows in the overall 4-bit pattern. Note that if the Response Agent stalls the Response Phase (because it doesn't have the response ready to be delivered yet), proper parity must be provided for each Idle response until the actual response is driven.
ChipSet Response Phase Parity Checking and Reporting
Refer to Figure 51-16 on page 1274. The example system shown is a PCI Express-based system and the device that connects the processors to the remainder of the system is referred to as the Root Complex. In a PCI or a PCI-X based system, it is referred to as the North Bridge or as the Memory Control Hub (MCH). The device that connects the processors to the remainder of the system is part of the chipset.
When a FSB agent other than the chipset (e.g., a processor) initiates a transaction on the FSB, the chipset may or may not check the Response Phase parity bit for correctness. Many chipsets designed for low- and medium- range systems do not. Some high-end chipsets, however, do check for correct Response Phase parity. The actions taken by such a chipset in the event of a Response Phase parity error is chipset design-specific. As an example, some high-end Intel® chipsets take the following actions:
The chipset receives the response (and its parity bit) it had initiated.
The chipset internally calculates the expected parity bit based on the response received.
The parity bit just latched is compared to the calculated parity bit:
- If they are the same, the response did not suffer in-flight corruption and the chipset will not report an error.
- If the calculated and actual parity bits disagree, the chipset causes an error signal to be asserted:
- In some chipsets, the ICH (IO Control Hub) chipset member is instructed to send an NMI (Non-Maskable Interrupt) to the processor. This causes the processor to execute the NMI handler routine which checks a chipset status register to determine the cause of the error, reports the error to the end-user, disables interrupt recognition and halts the processor.
- In some chipsets, the MCH asserts MCERR# (Machine Check Error) to the processor. This causes the processor to log an error in its Machine Check Architecture error logging registers and, if the processor is enabled to do so (via CR4[MCE]), generate a Machine Check exception. The MC handler is then executed and checks a chipset status register to determine the cause of the error, reports the error to the end-user, disables interrupt recognition and halts the processor.
Processor Response Phase Parity Checking and Reporting
Whether or not a processor is enabled to check the Response Phase parity when a FSB transaction is initiated by another agent is controller by bit 2 in the EBC_Soft_Poweron MSR (see Figure 51-17 on page 1275). If this capability is enabled, the processor takes the following actions:
The processor internally calculates the expected parity bit based on the response received.
The parity bit sampled is compared to the calculated parity bit:
- If they are the same, the response did not suffer in-flight corruption and the processor will not report an error.
- If the calculated and actual parity bits disagree, the processor logs the error as a hard failure (rather than as a correctable error) in its Machine Check Architecture error logging register set. If the processor is enabled to do so (via CR4[MCE]), it also generates a Machine Check exception.
