Chapter 48. Pentium^® 4 FSB Blocking

The Previous Chapter

This chapter described the FSB locking mechanism, the reason for its existence, and the instructions that invoke it. It included:

• The Shared Resource Concept.

• Testing the Availability of and Gaining Ownership of Shared Resources.

• A Race Condition Can Present a Problem.

• Guaranteeing the Atomicity of a Read/Modify/Write.

• Locking a Cache Line.

This Chapter

This chapter describes the mechanism that permits FSB agents to limit the number of transactions that can be injected into the FSB. It includes:

• Assert BNR# When One Entry Remains.

• BNR# Can Be Used by a Debug Tool.

• Who Monitors BNR#.

• BNR# is a Shared Signal.

• The Stalled/Throttled/Free Indicator.

• Initial Entry to the Stalled State.

• The Throttled State.

• The Free State.

• As an Agent Approaches Full, It Signals BNR# to Stall Everyone.

• BNR# Behavior at Powerup.

• BNR# Behavior During Runtime.

The Next Chapter

This chapters provides a detailed description of the Request Phase of a FSB transaction. It includes:

• Introduction to the Request Phase.

• The Source Synchronous Strobes.

• The Request Phase Parity.

• Request Phase Parity Checking.

• ChipSet Request Phase Parity Checking and Reporting.

• Processor Request Phase Parity Checking and Reporting.

• The Request Phase Signal Group is Multiplexed.

• Introduction to the Transaction Types.

• The Contents of Request Packet A.

• 32-bit vs. 36-bit Addresses.

• The Contents of Request Packet B.