A transaction that transferred data consisted of five phases:
The Request Phase. The Error Phase. The Snoop Phase. The Response Phase. The Data Phase
| The Error Phase was eliminated in the Pentium® 4's FSB protocol. |
| The Request Phase was two bus clock (BCLK) cycles in duration. | The Request Phase is one bus clock cycle in duration. |
| 8-bytes of data (i.e., a qword) could be transferred on each rising-edge of BCLK. It therefore took four BCLK cycles to transfer a 32-byte line. | 32 bytes of data can be transferred during each BCLK cycle. |
| Interrupt messages were transferred to and from a processor over the 3-wire APIC bus. | The APIC bus has been eliminated. Interrupt messages are transferred to and from a processor by performing memory write transactions on the FSB |
| BSP selection was made using an exchange of interrupt messages over the 3-wire APIC bus. | BSP selection is made using the FSB. |
| The GTL reference voltage was 2/3 of Vtt. | The GTL reference voltage is 2/3 of Vcc (+ or - 2%) rather than 2/3 of Vtt. |
| The Bus Error (BERR#) signal was used to report serious problems detected in a FSB transaction. | The BERR# signal was eliminated and replaced by the Machine Check Error (MCERR#) signal. |
| The RP# output signal was the parity bit for the processor's REQ[4:0]# and ADS# signal lines. | The RP# signal was eliminated and replaced by a different parity scheme. |
| All FSB agents latched Packets A and B of a transaction request on the rising-edges of two successive BCLK cycles. | Two new, high-speed address strobes, ADSTB[1:0]#, are now used to strobe the two packets into the receivers of FSB agents. |
| BCLK was a single signal line. | BCLK is now a differential signal pair consisting of BCLK[1:0]. |
| | The Data Bus Inversion feature has been added. |
| The 64-bit data bus was parity protected by eight parity signals, one for each of the eight byte-wide data paths. | The 64-bit data bus is now protected by four signals, one for each group of 16 data lines. |
| The device accepting data used the rising-edge of the BCLK to strobe the data into its input latch. | The device driving data also drives a series of data strobes that the receiving device uses to strobe the data into its input latch. This permits data to be transferred four times faster than the BCLK rate. |
| The AGTL+ signals that comprise the FSB must be terminated at either end by a pull-up resistor. In a P6-based system, the resistors were located on the system board. | The Pentium® 4 processor incorporates a pull-up resistor on each AGTL+ FSB signal. It also has an input that enables or disables the on-die termination resistors. |
| The largest data transfer that could be specified in a transaction was 32 bytes (one cache line). | The largest data transfer that can be specified is 64 bytes. |
