One Product Yields Three Product Lines

Soon after the advent of the Pentium® II product, Intel® divided the P6 into three product lines, two of which are just variations on the Pentium® II processor.

• The Pentium® II processor targeted the mid- to high-end desktop market and supported either one or two processors on the FSB.

• The Xeon processor. The Xeon targeted the workstation and server market and supported either two (in a Xeon DP product), or four (in a Xeon MP product) processors on the FSB. With the following exceptions, the Xeon was identical to the Pentium® II:

  - While all models of the Pentium® II had a 512KB L2 Cache, the Pentium® II Xeon was available with a 512KB, 1MB, or 2MB L2 Cache.

  - While the Pentium® II's BSB operated at 50% of the processor's core speed, the Pentium® II Xeon's BSB operated at 100% of the core speed.

  - The Xeon implemented a Processor Information ROM, a scratch EEPROM and a thermal diode that could all be read from over the serial SMBus.

  - The Pentium® II implemented two pins (BR[1:0]#) for FSB arbitration, permitting two processors on the FSB. The Xeon MP implemented four pins (BR[3:0]#), permitting four processors on the FSB.

• The Celeron processor. The Pentium® II Celeron targeted the low-end desktop market and only supported one processor on the FSB. With the following exceptions, the Celeron was identical to the Pentium® II:

  - The Pentium® II implemented two pins (BR[1:0]#) for FSB arbitration, permitting two processors on the FSB. The Celeron implemented one pin (BR0#), permitting one processor on the FSB.

  - The FSB speed (i.e., the BCLK frequency) of the Celeron was slower than that of the Pentium® II.