Chapter 41. Pentium^® 4 Handling of Loads and Stores

The Previous Chapter

This chapter provided a detailed description of the Pentium® 4 caches. This included:

• Determining the Processor's Cache Sizes and Structures.

• Enabling/Disabling the Caches.

• The L1 Data Cache.

• The L2 ATC.

• The Hardware Data Prefetcher.

• The L3 Cache.

• FSB Transactions and the Caches.

• The Cache Management Instructions.

This Chapter

This chapter provides a detailed description of load and store operations and includes:

• The Memory Type Defines Load/Store Characteristics.

• The Load Buffers.

• Loads from Cacheable Memory.

• Loads Can Be Executed Out-of-Order.

• The L1 Data Cache Implements Squashing.

• Loads from Uncacheable Memory.

• The Definition of a Speculatively Executed Load.

• Replay.

• Loads and the Prefetch Instructions.

• The LFENCE Instruction.

• Store-to-Load Forwarding.

• Stores Are Handled by the Store Buffers.

• Stores to UC Memory.

• Stores to WC Memory.

• Stores to WP Memory.

• Stores to WT Memory.

• Forcing a Buffer Drain.

• The SFENCE Instruction.

• Sharing Access to a UC, WC, WP or WT Memory Region.

• Stores to WB Memory.

• Out-of-Order String Stores.

• Stores and Hyper-Threading.

• The MFENCE Instruction.

• Non-Temporal Stores.

The Next Chapter

This chapter provides a complete description of the 90nm Prescott Pentium® 4 processor. This includes:

• Increased Pipeline Depth.

• Trace Cache Improvements.

• Increased Number of WCBs.

• L1 Data Cache Changes.

• Increased L2 Cache Size.

• Enhanced Branch Prediction.

• Store Forwarding Improved.

• SSE3 Instruction Set.

• Increased Elimination of Dependencies.

• Enhanced Shifter/Rotator.

• Integer Multiply Enhanced.

• Scheduler Enhancements.

• Fixed the MXCSR Serialization Problem.

• Data Prefetch Instruction Execution Enhanced.

• Improved the Hardware Data Prefetcher.

• Hyper-Threading Improved.