The Local APIC Register Set
Local and IO APIC Register Areas Are Uncacheable
As with all areas of memory populated by memory-mapped IO registers, the memory areas within which the Local and IO APIC's register sets reside must be designated as uncacheable (UC) memory in the MTRRs.
Introduction to the Local APIC's Register Set
Figure 61-16 on page 1525 illustrates the Local APIC's memory-mapped IO register set. In the Pentium® processor, the register set occupied a 4KB memory address range starting at location FEE00000h and the address range could not be altered. This constraint disappeared with the addition of the APIC_BASE MSR (see Figure 61-15 on page 1524; referred to as the IA32_APIC_BASE register starting with the Pentium® 4) in the Pentium® Pro processor. Using bits [35:12], the programmer can program the upper portion of the 4KB-aligned base address assigned to the register set. It should be noted that although a 4KB address range is set aside for the register set, the register set currently only occupies the lower 1KB of the assigned address range. The remaining 3KB block is reserved for possible future expansion.
Figure 61-15. The IA32_APIC_BASE MSR
Table 61-3 on page 1526 provides a brief description of each of the Local APIC registers. A comprehensive description of the registers can be found in the appropriate sections of this chapter.
| Register Name | Width (bits) | R/W? | Base Memory Address | Description |
|---|---|---|---|---|
| Local APIC ID Register | 32 | RW | FEE00020h | On the trailing-edge of reset, the Local APIC associated with each processor (or, in an HT-capable processor, with each logical processor) is assigned an APIC ID that is unique in the system. This ID can be changed by software (i.e., by the OS or by the BIOS). The ID is used as the address in an interrupt message to identify the Local APIC (and therefore processor) that is the target of the message. See “Local Cluster and APIC ID Assignment” on page 1513. |
| Local APIC Version Register | 32 | RO | FEE00030h | This read-only register contains the version of the Local APIC and the number of entries (minus 1) that it implements in its LVT. See “Detecting the Presence and Version of the Local APIC” on page 1509 and “The Local Vector Table” on page 1539. |
| Task Priority Register (TPR) | 32 | RW | FEE00080h | This mechanism enables the OS scheduler to prevent specific interrupts (generally low-priority interrupts) from disturbing high-priority work that the processor is doing. Whenever the OS scheduler instructs the processor to start executing a task, the OS causes a value to be written into the Local APIC's TPR. This permits the scheduler to set a priority threshold for interrupting the processor. The processor only services only those interrupts that have a priority higher than that specified in the TPR. If the scheduler sets the task priority in the TPR to 0, the processor recognizes all interrupts, while setting it to 15 prevents the processor from handling all interrupts except NMI, SMI, INIT, ExtINT, INIT-deassert, and SIPI. See “Locally Generated Interrupts” on page 1539 for more information. |
| Arbitration Priority Register (APR) | 32 | RO | FEE00090h | This read-only register was implemented in the Pentium® and P6 processors, but was eliminated in the IA32 processors starting with the Pentium® 4 processor (because the 3-wire APIC bus was eliminated). When an interrupt message specifying Lowest-Priority delivery mode was received, the Local APICs compared their APR values on the APIC bus to determine which of the processors was currently executing the lowest-priority (and therefore the most interruptible) task. That Local APIC would then deliver the interrupt to its respective processor core. See chapter 15 of the MindShare book entitled Pentium® Processor System Architecture, Second Edition for more information. |
| Processor Priority Register (PPR) | 32 | RO | FEE000A0h | When interrupts are pending in the IRR and ISR registers, the Local APIC dispatches them to the processor core one at a time, based on:
|
| EOI Register | 32 | WO | FEE000B0h | After the body of an interrupt handler for any interrupt except NMI, SMI, INIT, ExtINT, SIPI, or INIT Deassert has completed servicing the interrupt request, the handler must perform a memory-mapped IO write of zero to the Local APIC's End-of-Interrupt (EOI) register before executing the IRET instruction at the end of the handler. Upon receipt of the EOI, the Local APIC clears the highest-priority bit that is currently set to one in the ISR (this bit corresponds to the interrupt that was just serviced). It then clears the highest-priority bit that is currently set in the IRR, sets the corresponding bit in the ISR, and dispatches that interrupt to the processor core for servicing. If the interrupt just serviced was a level-triggered interrupt, the Local APIC also sends an EOI message to all IO APICs. See “The IRR, TMR and ISR Registers” on page 1535 for more information. |
| Logical Destination Register (LDR) | 32 | RW | FEE000D0h | When an interrupt message specifies Logical Destination Mode, the target Local APIC(s) are specified using an 8-bit Message Destination Address (MDA) that was written to the Destination field in the source Local APIC's ICR. Upon message receipt, the target Local APIC(s) compare the MDA in the message with the values in their LDR and DFR to determine if they should accept and handle the message. See “Logical Destination Mode” on page 1562 for more information. |
| Destination Format Register (DFR) | 32 | FEE000E0h | Bits [27:0] are read-only. Bits [31:28] are read/write and specify the system's APIC distribution model (Flat or Clustered Model). Upon receipt of a message that specifies Logical Destination Mode, the Local APIC uses the DFR value to properly interpret the message's MDA field (see the description of the LDR in this table). See “Logical Destination Mode” on page 1562 for more information. | |
| Spurious Interrupt Vector Register | 32 | FEE000F0h | Bits [8:0] are read/write and bits [31:9] are read-only. This register controls the following Local APIC features:
| |
| In-Service Register (ISR) | 256 | RO | FEE00100h | The bits that are set to one in the 256-bit, read-only ISR indicate all of the user-defined interrupts that are currently being serviced. As the servicing of each is completed, the associated ISR bit is cleared to 0. See “The IRR, TMR and ISR Registers” on page 1535 for more information. |
| Trigger Mode Register (TMR) | 256 | RO | FEE00180h | The bits in this 256-bit, read-only register correspond to the user-defined interrupt vectors and indicate whether each of the respective interrupts are edge- triggered or level-sensitive:
0 = Edge-triggered. 1 = Level sensitive. See “The IRR, TMR and ISR Registers” on page 1535 for more information. |
| Interrupt Request Register (IRR) | 256 | RO | FEE00200h | The bits in this 256-bit, read-only register correspond to the user-defined interrupt vectors. Upon receipt of an interrupt message containing a user-defined interrupt vector, the Local APIC sets the corresponding IRR bit to one. See “The IRR, TMR and ISR Registers” on page 1535 for more information. |
| Error Status Register (ESR) | 32 | RO | FEE00280h | When the Local APIC detects an error in a message to be sent or one that has been received, it sets the appropriate error bit in the ESR and, if enabled to do so (in the LVT Error entry), generates an interrupt to invoke the Local APIC's error handler. See “The Local APIC's Error Interrupt” on page 1549 for more information. |
| Interrupt Command Register (ICR) [0:31] | 32 | RW | FEE00300h | This 64-bit register consists of an upper half and a lower half. The software executing on a processor can stimulate its Local APIC to send an IPI to another processor by writing to the Local APIC's ICR. The programmer first writes to the upper half and then writes the remaining information to the lower half. The write to the lower half of the ICR triggers the Local APIC to send the message defined by the information in the ICR. See “Sending a Message From the Local APIC” on page 1556. |
| Interrupt Command Register (ICR) [32:63] | 32 | RW | FEE00310h | |
| Local Vector Table Entries | ||||
| LVT Timer Register | RW | FEE00320h | These registers control the programmable timer incorporated within the Local APIC. It can be programmed to generate a single interrupt after a programmed amount of time, or to generate an interrupt on a periodic basis at a programmed interval. See “The Local APIC Timer” on page 1544 for more information. | |
| Initial Count Register (for Timer) | 32 | RW | FEE00380h | |
| Current Count Register (for Timer) | 32 | RO | FEE00390h | |
| Divide Configuration Register (for Timer) | 32 | RW | FEE003E0h | |
| LVT Thermal Sensor Register | 32 | RW | FEE00330h | |
| LVT Performance Monitoring CountersRegister | 32 | RW | FEE00340h | This register is used to enable or disable the Performance Counter logic to generate an interrupt on counter overflow. See “The Performance Counter Overflow Interrupt” on page 1547 for more information. |
| LVT LINT0 Register | 32 | RW | FEE00350h | Defines an interrupt to be delivered to the processor when the processor's LINT0 pin is asserted. See “Local Interrupt 0 (LINT0)” on page 1540 for more information. |
| LVT LINT1 Register | 32 | RW | FEE00360h | Defines an interrupt to be delivered to the processor when the processor's LINT1 pin is asserted. See “Local Interrupt 1 (LINT1)” on page 1543 for more information. |
| LVT Error Register | 32 | RW | FEE00370h | Defines an interrupt to be delivered to the processor when the Local APIC detects an error condition. See “The Local APIC's Error Interrupt” on page 1549 for more information. |
The IRR, TMR and ISR Registers
General
Refer to Figure 61-17 on page 1538. When a user-defined interrupt is received by the Local APIC, the vector number is used to select an entry in the Interrupt Request Register (the IRR). That IRR bit is set to one to record the fact that the interrupt requires servicing. Simultaneously, the vector number also selects an entry in the Trigger Mode Register (the TMR). Upon acceptance of the interrupt into the IRR, the corresponding TMR bit is:
Cleared if the interrupt is an edge-triggered interrupt, or
Set if the interrupt is a level-sensitive interrupt.
Figure 61-17. The IRR, TMR and ISR Registers
Based on the user-defined interrupt priority scheme (see Table 61-2 on page 1520), the Local APIC selects the highest-priority IRR bit that is set to one. It clears that IRR bit to zero and sets the corresponding bit in the ISR to one. Setting the ISR bit to one signifies that the interrupt is currently being serviced by the processor. It then dispatches the interrupt vector associated with the highest-priority ISR bit that is set to one to the processor for servicing.
The user-defined interrupt selects an entry in the IDT and that entry contains one of the following:
An Interrupt Gate descriptor. The processor first stores the current EFlags register contents in stack memory. It then clears EFlags[IF] to disable recognition of additional user-defined interrupts while in the body of the interrupt handler. The execution of the IRET instruction at the end of the handler causes the EFlags image to be popped from the stack back into the EFlags register, thereby automatically re-enabling recognition of user-defined interrupts. It should be noted that the execution of an STI instruction while in the body of the handler will re-enable recognition of user-defined interrupts.
A Trap Gate descriptor. Accessing a handler procedure through a Trap Gate does not change the state of EFlags[IF], so recognition of additional user-defined interrupts remains enabled.
An Example
Assume that user-defined interrupt vector 3210 requires service. IRR bit 32 is set to one to reflect this fact.
When 32 is the highest-priority user-defined interrupt requiring service, the Local APIC sets bit 32 in the ISR and clears bit 32 in the IRR.
It then dispatches interrupt vector 32 to the processor for servicing.
The currently executing program is interrupted. The processor automatically pushes the contents of the CS, EIP and EFlags registers into stack memory.
Assume either that IDT entry 32 contains a Trap Gate descriptor, or that it contains an Interrupt Gate descriptor but that the interrupt handler executes an STI instruction to re-enable recognition of user-defined interrupts.
While the interrupt 32 handler is executing, the Local APIC will queue but not service any lower-priority user-defined interrupts that may be received.
Assume that user-defined interrupt 4010 is delivered to the Local APIC. Bit 40 is set to one in the IRR and, because it has a higher-priority than 32 and interrupt recognition is still enabled, the Local APIC takes the following actions.
It sets bit 40 in the ISR and clears bit 40 in the IRR.
Bits 32 and 40 are now both set in the ISR.
It then dispatches interrupt vector 40 to the processor for servicing.
The interrupt 32 handler is interrupted. The processor automatically pushes the contents of the CS, EIP and EFlags registers in stack memory. The saved CS:EIP pointer points to the next instruction that would have been executed in the interrupt 32 handler if it had not been interrupted.
Using the start address specified in IDT entry 40, the processor jumps to and begins executing the interrupt 40 handler.
The EOI and Its Effects
After the interrupt handler for a user-defined interrupt has completed servicing the interrupt, the handler performs a memory write of 00h to the Local APIC's End-of-Interrupt (EOI) register. The data written to the register must be zero. In response, the Local APIC takes the following actions:
If the TMR bit associated with the highest-priority one bit in the ISR is set to one (indicating that this was a level-sensitive interrupt), the Local APIC writes the interrupt's vector number to the IO APIC's EOI register. See “The EOI Register” on page 1578 and “Overview of a Level-Sensitive Interrupt Delivery” on page 1571 for a complete description.
It clears the highest-priority bit that is currently set to one in the ISR (because it has completed servicing that interrupt).
It clears the highest-priority bit in the IRR (because it is about to start servicing that interrupt).
It sets the corresponding bit in the ISR (to signify it is now servicing that interrupt).
It dispatches the interrupt vector associated with the highest-priority ISR bit that is set to one to the processor for servicing.
The processor core then begins executing that interrupt handler.
Interrupt Request Buffering
As described earlier, on receipt of a user-defined interrupt the Local APIC sets the respective bit in its IRR. When that user-defined interrupt is the highest-priority pending request, the Local APIC sets the respective bit in the ISR and clears the IRR bit. The IRR bit is therefore ready to receive and register another user-defined interrupt with the same vector.
On the Pentium® 4 family processors, the Local APIC can buffer two requests per vector: the one that is currently being serviced (as indicated by the ISR bit being set to one), and another awaiting service (as indicated by the IRR bit being set to one). If the Local APIC should receive another user-defined interrupt with the same vector while both of these bits are set to one, the newly-received request is discarded.
On the P6 and Pentium® family processors, the IRR and ISR registers can queue no more than two interrupts per priority level (i.e., per group of 16 interrupt vectors). Any additional interrupts within the same group of 16 are ignored.
Register Access Alignment
To modify a field (e.g., a bit or a byte) in any of the Local APIC's registers, the entire 32-bit register is read, the appropriate field(s) are modified, and a 32-bit write is done to update the register. Support for partial or non-aligned register access can vary from one implementation to another. 64-bit registers must be accessed as two, 32-bit registers.