The Bus and Processor Clocks

The BSEL Outputs

Each model of Pentium® 4 processor is designed to operate at a certain internal clock frequency as well as a FSB frequency. A clock generator on the system board generates the Bus Clock (BCLK) to the processor(s) and all other FSB agents. The processor provides two outputs, BSEL[1:0], that are connected to the system board's clock generator and the 2-bit pattern that is output on these two signals tells the clock generator the frequency of the BCLK to be supplied to all FSB agents. Table 43-1 on page 1117 defines the possible settings on the processor's BSEL[1:0] outputs. Currently, the Pentium® 4's FSB has a BCLK speed of 200MHz.

Table 43-1. BSEL Truth Table
BSEL1BSEL0BCLK Frequency Required
00100MHz.
01133MHz.
10200MHz.
11Reserved.

The Processor's Operational Clock Frequency

The processor derives its internal clock from the BCLK frequency. BCLK is provided as an input to a PLL (Phase-Locked Loop) within the processor. The PLL multiplies the BCLK frequency by a factory preset multiplier value to yield the internal processor clock.

BCLK Is a Differential Signal

All signaling on the FSB is synchronized to the Bus Clock (BCLK). While this function was fulfilled by one signal line (BCLK) on the P6 FSB, it is now a differential signal pair comprised of the BCLK[1:0] signals (see Figure 43-1 on page 1118).

Figure 43-1. BCLK Is a Differential Signal


All FSB timing parameters are specified with respect to the rising-edge of BCLK0 crossing VCROSS (i.e., the point where the voltage level on BCLK0 and BCLK1 are equal).

Common clock signals are driven or are sampled when the rising-edge of BCLK0 crosses VCROSS. They are listed in Table 43-2 on page 1118.

Table 43-2. Signals that Are Synchronous to BCLK[1:0]
Signal Name(s)Description
BPRI#Bus Priority Agent Request.
DEFER#The Defer or Retry signal.
RESET#The Hard Reset signal.
RS[2:0]#The Response bus.
RSP#The parity bit for the Response bus.
TRDY#Target Ready.
AP[1:0]#The Request Phase parity bits for packets A and B.
ADS#Address Strobe.
BINIT#Bus Initialization.
BNR#Block Next Request.
BPM[5:0]#Breakpoint/Performance Monitor output pins.
BR0#The Bus Request output.
DBSY#Data Bus Busy.
DP[3:0]#The Data Bus parity bits.
DRDY#Data Ready.
HIT#

  • If HIT# is asserted but HITM# is not, signals a Hit on an unmodified line.

  • If both HIT# and HITM# are asserted, signals a Snoop Stall condition.

HITM#

  • If HITM# is asserted but HIT# is not, signals a Hit on a modified line.

  • If both HIT# and HITM# are asserted, signals a Snoop Stall condition.

LOCK#Asserted during a locked read/modify write operation.
MCERR#The Machine Check Error output.
ADSTB[1:0]#The Request Phase strobes.
DSTBP[3:0]#, DSTBN[3:0]#The Data Phase strobes.

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