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Acronyms

Term	Description
A/D	Analog-to-Digital converter.
AC	Alignment Check.
AC '97 Link	Audio Codec (AC) '97 Link.
ACPI	Advanced Configuration and Power Interface.
AF	Auxiliary Carry bit in the EFlags register.
AGP	Accelerated Graphics Port.
AGTL+	Assisted Gunning Transceiver Logic Plus.
ALU	Arithmetic Logic Unit.
AM	The Alignment Mask bit in CR0.
AOS	Array of Structures.
AP	Application Processor (as opposed to Boot Strap Processor).
APIC	Advanced Programmable Interrupt Controller.
APR	Arbitration Priority Register.
ASZ	Address Size field in a FSB transaction.
ATC	Advanced Transfer Cache (the L2 Cache).
ATTR[7:0]	The Attribute signals indicate the type of memory (UC, WC, WP, WT or WB) being addressed in a FSB transaction.
B	The Busy bit in a TSS descriptor. The Big bit in a Stack segement descriptor.
BBL	Back Side Bus Logic that connects the L2 Cache to the processor core.
BCLK	FSB Bus Clock.
BE[7:0]	The processor's Byte Enable outputs: Indicates the bytes being addressed in a memory, IO, or BTM transaction. Indicates the message type in a Special transaction.
BGA	Ball Grid Array package.
BIOS ROM	Binary Input Output System Read-Only Memory.
BIOS Update	This refers to the Microcode Update feature implemented in the P6 and Pentium® 4 processor families.
BIPI	Bootstrap Inter Processor Interrupt message (only applies to the P6 processor family).
BIST	Built-In Self-Test.
BOS	Bottom of Stack.
BPU	Branch Prediction Unit.
BSB	The Back Side Bus that connects the L2 Cache to the processor core.
BSP	Boot Strap Processor.
BSQ	Bus Sequence Queue (another name for the processor's FSB Interface Unit).
BSU	Bus Sequence Unit (another name for the processor's FSB Interface Unit).
BTB	Branch Target Buffer. This is the dynamic branch predictor that maintains branch history.
BTM	Branch Trace Message transaction.
BTS	Branch Trace Store feature.
Byte	8-bits.
C	The Conforming bit in a code segment descriptor.
C/D	The Code or Data bit in a non-system segment descriptor.
CCCR	Counter Configuration Control Regtister.
CC[3:0]	The Condition Code bits in the FSW register.
CD	The Cache Disable bit in CR0.
CESR	Counter Event Select Register.
CF	The Carry Flag bit in the EFlags register.
CID	Context ID.
CISC	Complex Instruction Set Computer.
CMOS	Complementary Metallic Oxide.
CMP	Chip Multiprocessing.
CPI	Clocks per Instruction.
CPL	Current Privilege Level.
CR	Control Register.
CR0	Control Register 0.
CR2	Control Register 1.
CR3	Control Register 3.
CR4	Control Register 4.
CRU	Cache References Unit.
CS	Code Segement register.
CWR	x87 FPU's Control Word Register.
D/B	Default or Big bit in a non-system segment descriptor.
DAC	Data cache Access Control unit.
DAT	The IO APIC's Data register.
DAZ	The Denormals Are Zeros bit in the MXCSR.
DDR	Double Data Rate memory.
DE	The Debug Extensions bit in CR4. The Denormal operand error bit in the x87 FPU's Status register. The Denormal operand error bit in the MXCSR.
DEP	Double Extended Precision 80-bit FP number.
DF	The Direction Flag bit in the EFlags register.
DFR	The Destination Format Register.
DIBA	Dual Independent Bus Architecture.
DID	Deferred ID.
DMA	Direct Memory Access.
DNA	The Device Not Available exception.
Double Qword	16 bytes starting on an address divisible by 16.
DP	A 64-bit Double Precision FP number.
DPL	Data Prefetch Logic (refers to the hardware-based prefetcher that prefetches data into the processor's top-level cache.
DR6	The Debug Status register.
DR7	The Debug Control register.
DR[3:0]	The four Debug breakpoint address registers.
DR[7:0]	The Debug register set.
DS	The debug store feature. The Data Segment register.
DSE	The Dedicated Stack Engine.
DTLB	The Data Translation Lookaside Buffer.
Dword	A 32-bit data object.
EBC	External Bus Control (refers to the FSB control logic).
EBL	External Bus Logic (refers to the FSB Interface Unit).
EBP	Extended Base Pointer register.
ECC	Error Code Correcting memory.
EDI	Extended Destination Index register.
EEPROM	Electrically Eraseable Programmable Read-Only Memory.
EEROM	Electrically Eraseable Read-Only Memory.
EFlags	Extended Flags register.
EIP	Extended Instruction Pointer register.
EIPV	Error Instruction Pointer Valid bit.
EM	The FL Emulation bit in CR0.
EMSB	Enhanced Mode Scaleable Bus (i.e., the FSB).
EOI	End-of-Interrupt.
EOIR	End-of-Interrupt Register.
ES	The E Data Segment register.
ESCR	Event Select Control Register.
ESI	Extended Source Index register.
ESMA	Extended Server Memory Architecture.
ESP	Extended Stack Pointer register.
ESP0	The Privilege Level 0 Extended Stack Pointer field in a TSS.
ESP1	The Privilege Level 1 Extended Stack Pointer field in a TSS.
ESP2	The Privilege Level 2 Extended Stack Pointer field in a TSS.
ESR	Error Status Register.
EST	Enhanced SpeedStep Technology.
ET	The x87 FP Extension Type bit in CR0.
EXT	The External event bit in an exception error code pushed onto the stack.
FEU	FP Execution Unit.
FIPI	Final Inter Processor Interrupt message (only applies to the P6 processor family).
FLOPs	FP Operations Per second.
FP	Floating-Point.
FPU	Floating-Point Unit.
FRC	Functional Redundancy Check.
FS	F Data Segment register.
FSB	Front Side Bus.
FTZ	The Flush To Zero bit in the MXCSR.
G	The Global bit in a PTE.
G0	Enable global breakpoint 0.
G1	Enable global breakpoint 1.
G2	Enable global breakpoint 2.
G3	Enable global breakpoint 3.
GB	Gigabytes (2³¹).
GD	General Detect condition. Occurs if an instruction attempts to access a Debug register while they are being used by a debug tool.
GDT	Global Descriptor Table.
GDTR	Global Descriptor Table Register.
GE	The Global Enable bit in DR7.
GFX	Graphics Adapter.
GP	General Protection exception.
GPRs	General Purpose Registers.
GS	The G Data Segment register.
GTL+	Gunning Transceiver Logic Plus.
HFM	High-Frequency Mode.
HI	Hub Interface.
HMA	High-Memory Area.
HT	Hyper-Threading.
HTT	Hyper-Threading Technology.
IA	Intel® Architecture.
IA32	32-bit Intel® Architecture.
IA32e	One of the names that refers to the 64-bit extensions implemented in IA32 processors. The official name is now Intel® Extended Memory 64 Technology.
IC	The Infinity Control bit in the FCW register.
ICE	In-Circuit Emulator.
ICH	IO Control Hub.
ICR	Interrupt Command Register.
IDE	Integrated Drive Electronics.
IDT	Interrupt Descriptor Table.
IDTR	Interrupt Descriptor Table Register.
IE	The Invalid operation error bit in the FSW register.
IF	The Interrupt Flag bit in the EFlags register.
IFU	Instruction Fetch Unit.
ILP	Instruction Level Parallelism.
IMVP	Intel® Mobile Voltage Positioning.
IND	The IO APIC's Index register.
INTR	Interrupt Request.
IO	Input/Output.
IO APIC	IO Advanced Programmable Interrupt Controller.
IOPL	The 2-bit IO Privilege Level field in the EFlags register.
IOQ	In-Order Queue.
IP	The 16-bit Instruction Pointer register.
IPI	Inter Processor Inetrrupt message.
IQ	Instruction Queue.
IRQ	Interrupt Request.
IRQPA	Interrupt Request Pin Assertion register in the IO APIC module.
IRR	Interrupt Request Register in the Local or IO APIC.
ISA	Instruction Set Archiecture. Refers to the IA instruction set. Industry Standard Architecture. Refers to the old ISA bus in PCs.
ISR	In-Service Register in the Local or IO APIC.
ISSE	Internet Streaming SIMD Extensions. Refers to the SSE instruction and register sets.
ITLB	Instruction Translation Lookaside Buffer.
KNI	Katmai New Instructions. The code name for the SSE instruction set.
L0	The Enable local breakpoint 0 bit in DR7. In some Intel® documentation, refers to the Data Cache.
L1	The Enable local breakpoint 1 bit in DR7. Refers to the L1 Data Cache or the L1 Code Cache.
L2	The L2 Cache.
L3	The L3 Cache.
LAN	Local Area Network.
LCI	LAN Controller Interface.
LDR	The Logical Destination Register in the Local APIC.
LDT	Local Descriptor Table.
LDTR	Local Descriptor Table Register.
LE	The 386 processor used this bit in DR7 as a master enable for the local enable bits associated with each breakpoint.
LEN	The data transfer length field in a FSB transaction request.
LFM	Low-Frequency Mode.
LGA	Land Grid Array. A package type.
LIFO	Last-In First-Out.
LINT0	Local Interrupt pin 0.
LINT1	Local Interrupt pin 1.
Local APIC	Local Advanced Programmable Interrupt Controller.
LPC	Low Pin Count bus.
LRU	Least-Recently Used.
lsb	least-significant bit.
LSB	Least-Significant Byte.
LVS	Low-Voltage Swing.
LVT	Local Vector Table.
M	Modified line.
MB	Megabytes (2²⁰).
MC	Machine Check.
MCA	Machine Check Architecture.
MCE	Machine Check Exception enable bit in CR4.
MCH	Memory Control Hub.
MDA	In the old days, the Monochrome Display Adapter. Message Destination Address.
ME	Motion Estimation.
MESI	Modified, Exclusive, Shared, Invalid.
MMX	Multi-Media Extensions or Matrix Math Extension. Take your pick. Intel® has never said what it means.
MM[7:0]	MMX registers 0 through 7.
MOB	Memory Order Buffer.
MP	Multiprocessing.
MPS	Multiprocessor Specification.
MRI	Memory Read and Invalidate transaction.
MRM	Most-Recent Master.
ms	milliseconds.
MS ROM	Microcode Store ROM.
Msb	most-significant bit.
MSB	Most-Significant Byte.
MSI	Message Signalled Interrupt.
MSRs	Model-Specific Registers.
MSW register	Machine Status Word Register. This is the lower 16 bits of CR0.
MT	Multiprocessing Table. Multi-Threading state.
MTRRs	Memory Type and Range Registers.
MXCSR	MMX/SSE Control/Status Register.
NA	Not Applicable.
NE	Numeric Exception bit in CR0.
nm	nano-meters.
NMI	Non-Maskable Interrupt.
NOP	No Operation.
NPEBS	Non-Precise Event-Based Sampling.
ns	nano-seconds.
NT	The Nested Task bit in the EFlags register.
NVRAM	Non-Volatile Random Access Memory.
NW	The Not Write Through bit in CR0.
OE	The numeric Overflow error bit in the FSW register.
OEM	Other Equipment Manufacturer.
OF	The Overflow flag bit in the EFlags register.
OOO	Out-of-Order execution.
OSFXSR	A bit in CR4 that indicates whether or not the OS supports the FP/SSE Save and Restore instructions and the SSE instruction set.
OSXMMEXCPT	A bit in CR4 that indicates whether or not the OS supports the SSE FP exception.
P	The Page Present bit in a PTE. The Page Present bit in a PDE. The Segment Present bit in a segment descriptor. The Present bit in a Page Fault exception error code pushed onto the stack.
P5	The code name for the original Pentium® processor.
P54C	The code name for the first Pentium® processor that incorporated a Local APIC module.
P55C	The code name for the first Pentium® processor to include MMX.
P6	The code name for the Pentium® Pro processor. All Pentium® Pro, Pentium® II and Pentium® III processors (including Celerons and Xeons) were members of the P6 processor family.
PAE-36	Physical Address Extension 36-bit.
PAT	Page Attribute Table.
PBE	Pending Break Enable.
PC	Pin Control bits in the Pentium®'s CESR. The Precision Control bit in the FCW register.
PCD	Page Cache Disable.
PCE	The Performance Counter Enable bit in CR4.
PCI	Peripheral Component Interface.
PCI Express	The network fabric version of PCI.
PCI-X	An enhanced verion of PCI.
PD	Page Directory.
PDBR	Page Directory Base Address Register (CR3).
PDE	Page Directory Entry.
PDPT	Page Directory Pointer Table.
PDPTE	Page Directory Pointer Table Entry.
PE	The Protected Mode Enable bit in CR0. The Precision Error bit in the FSW register. The Precision Error bit in the MXCSR.
PEBS	Precise Event Based Sampling.
PF	The parity Flag bit in the EFlags register.
PG	The Paging enable bit in CR0.
PGA	Pin Grid Array. A package type.
PGE	The Page Global Enable bit in CR4.
PIC	Programmable Interrupt Controller (refers to the 8259A PIC).
PIROM	Processor Information ROM.
PLL	Phase-Locked Loop.
PNI	Prescott New Instructions. The code name for the SSE3 instruction set.
POST	Power-On Self-Test.
PPR	Processor Priority Register.
PS	The 4MB (or 2MB) Page Size bit in a PDE.
PSE	The 4MB Page Size bit in CR4.
PSE-36	Page Size Extension 36-bit mode.
PSN	Processor Serial Number.
PT	Page Table.
PTE	Page Table Entry.
PVI	Protected Mode Virtual Interrupt.
PWB	A Posted Memory Write Buffer.
PWT	The Page Write-Through bit in CR3. The Page Write-Through bit in a PDE. The Page Write-Through bit in a PTE.
QNaN	Quite Not-a-Number.
Qword	A quadword is a group of eight bytes (typically aligned on a memory address divisible by eight).
R	The Data Read bit in a Code Segment descriptor.
R/W	The Read/Write bit in a Data Segment Descriptor. The Read/Write bit in a PDE. The Read/Write bit in a PTE. The Read/Write field in DR7. The Read/Write bit in the MSR_EBC_SOFT_POWERON MSR.
RAID	Redundant Array of Inexpensive Drives.
RAT	The Register Alias Table.
RC	The Rounding Control field in the FCW register. The Rounding Control field in the MXCSR.
REDIR_TBL	The Interrupt Redirection Table entries in the IO APIC.
REP	The Repeat instruction prefix.
RF	The Resume Flag bit in the EFlags register.
RFO	Read-For-Ownership. This is another name for the MRI transaction (as is RWITM).
RISC	Reduced Instruction Set Computer.
RMW	A Read-Modify-Write operation on a memory semaphore.
RO	Read-Only.
ROB	The ReOrder Buffer.
ROM	Read-Only Memory.
RPL	The Requester Privilege Level field in a segment register in Protected Mode.
RSB	Return Stack Buffer.
RT	The IO APIC's Interrupt Redirection Table.
RTC	The Real-Time Clock.
RWITM	Read With Intent To Modify. Another name for the MRI transaction (as is the RFO).
SCI	System Control Interrupt.
SCSI	Small Computer System Interface.
SE	The Summary Error bit in the FSW register.
SEC	Single-Edge Cartridge.
SF	The Sign Flag bit in the EFlags register. The Stack Fault bit in the FSW register.
SIMD	Single Instruction operating on Multiple Data items.
SIO	System IO chip.
SIPI	Startup Inter Processor Interrupt message.
SM Mode	System Management Mode.
SMBus	System Management Bus.
SMC	Self-Modifying Code.
SMI	System Management Interrupt.
SMM	System Management Mode.
SMP	Symmetric Multiprocessing.
SMT	Simultaneous Multi-Threading (aka Hyper-Threading).
SNaN	Signalling Not-a-Number.
SOA	Structure of Arrays.
SP	A 32-bit Single-Precision FP number.
SRAM	Static Random Access Memory.
SS	Stack Segment or Self-Snoop.
SS0	The privilege level 0 Stack Segment field in a TSS.
SS1	The privilege level 1 Stack Segment field in a TSS.
SS2	The privilege level 2 Stack Segment field in a TSS.
SSE	Streaming SIMD Extensions.
SSE2	Streaming SIMD Extensions 2.
SSE3	Streaming SIMD Extensions 3.
ST0	Single Thread executing on logical processor 0.
ST1	Single Thread executing on logical processor 1.
ST[7:0]	x87 FPU's eight data registers.
SVR	Spurious Vector Register in the Local APIC.
SWR	x87 FPU's Status Word Register.
T	The debug Trap bit in a TSS.
TAP	The Test Access Port.
TC	The Trace Cache.
TDE	The Trace Delivery Engine.
TF	The Trap Flag in the EFlags register.
TI	The Table Indicator bit in a segment register in Protected Mode.
TLB	Translation Lookaside Buffer.
TLP	Thread-Level Parallelism.
TM and TM2	The Thermal Monitor. The Thermal Monitor 2 (in the Pentium® M processor).
TMR	The Trigger Mode Register in the Local APIC.
TOS	Top-of-Stack.
TPR	Task Priority Register.
TR	The Task Register. The Branch Trace Messaging enable bit in the DEBUGCTL MSR.
TSC	The Time Stamp Counter register.
TSD	The Time Stamp Disable bit in CR4.
TSS	Task State Segment.
TWR	The x87 FPU's Tag Word Register.
U	Refers to the “U” instruction pipeline in the Pentium® processor.
U/S	The User/Supervisor bit in a PDE. The User/Supervisor bit in a PTE.
UC	The Uncacheable memory type.
UE	The Underflow Error bit in the FSW register. The Underflow Error bit in the MXCSR.
USB	Universal Serial Bus.
V	Refers to the “V” instruction pipeline in the Pentium® processor.
Vcc	The processor die's operating voltage (common collector voltage).
VER	The IO APIC's Version Register.
VGA	Video Graphics Adapter.
VID	The processor's Voltage ID outputs to the voltage regulator on the system board.
VIF	The Virtual Interrupt Flag bit in the EFlags register.
VIP	The Virtual Interrupt Pending bit in the EFlags register.
VM	Short for Virtual 8086 Mode.
VM86 Mode	Virtual 8086 Mode.
VME	The Virtual 8086 Mode Extensions bit in CR4.
VMM	The Virtual Machine Monitor program.
Vref	The reference voltage for FSB input comparators.
Vss	Ground.
Vtt	Terminal voltage for the FSB AGTL+ signals.
W	The Write bit in a data segment descriptor.
WB	The cacheable WriteBack memory type.
WC	The non-cacheable Write-Combining memory type.
WCB	Write Combining Buffer.
Word	A 16-bit data object.
WP	The cacheable Write-Protected memory type.
WT	The cacheable Write-Through memory type.
X	In a Call Gate descriptor, the X bit defines it as a 16-bit or a 32-bit Call Gate.
xAPIC	The improved APIC used in the Pentium® 4 processor family (and in the Itanium processors, as well).
XMM[7:0]	SSE data registers 0 through 7.
XTP	The External Task Priority registers in the chipset.
ZE	The Divide-by-Zero Error bit in the FSW register.
ZF	The Zero Flag bit in the EFlags register.
μop	A micro-op (i.e., a fixed-length RISC instruction executed by the processor core in a P6 or Pentium® 4 processor.

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