Speculative Execution

As mentioned earlier, the Pentium® 4 processor can execute instructions speculatively (as could the P6 processor). The Pentium® 4 processor can speculatively execute instructions that reside downstream of a conditional branch instruction before the branch has been executed. Consider the following code fragment:

      ---
      ---
      Jcc  bypass
      ---
      mov  eax,[0100]    ;read could be executed before Jcc
      ---
      mov  ecx,es:[1234] ;this one as well
bypass

The processor could execute the four instructions beneath the conditional branch and then execute the branch. However, remember that the results of an μop's execution are not stored in the actual processor register set. Rather, they are stored in alias registers. If when the branch is finally executed, it is discovered that the branch is taken, the processor core merely discards the contents of the alias registers associated with the four μop's that were speculatively executed.

It should be noted that, in the example code fragment, two of the speculatively executed instructions are loads (i.e., memory data reads). Whether or not the processor is permitted to speculatively execute load instructions is determined by the type of memory that would be read from. Speculative execution of loads is not permitted in UC (Uncacheable) memory, but it is permitted in WC (Write Combining), WP (Write Protected), WT (Write Through) and WB (Write Back) memory. As an example, the processor must not be permitted to speculatively perform a load from a memory-mapped IO status port wherein reading from the port would cause the device adapter to clear any error bits that might be set.