Assignment of IDs to the Processor
Introduction
At power-up time, each of the processors on the FSB must be assigned a unique ID that is output in any transaction initiated by the processor. This is referred to as its Agent ID. In addition, each processor contains a Local APIC module. This module must be assigned two addresses at startup time: a Cluster ID and a Local APIC ID.
The Cluster ID
The Purpose of the Cluster ID
In the Pentium® 4 processor family, interrupt messages are transferred over the FSB (the 3-wire APIC bus was eliminated). An interrupt message contains a destination address and one of the forms it can take is that of a Cluster ID and the ID of a Local APIC within a processor in the target cluster. For this reason, a Cluster ID is assigned to each processor's Local APIC on the removal of reset. The IO APIC may generate an interrupt message specifying delivery to a specific processor within a specific cluster.
The Cluster ID Assignment
The Cluster ID identifies what cluster of processors the processor (and therefore its encapsulated APIC) is a member of. See Figure 36-5 on page 861. The processor may be assigned a cluster number of 0, 1, 2, or 3. A[12:11]# are sampled at the trailing-edge of reset to determine the cluster ID:
Sampled electrical value 00b = cluster 3.
Sampled electrical value 01b = cluster 2.
Sampled electrical value 10b = cluster 1.
Sampled electrical value 11b = cluster 0.
The Agent ID
The Purpose of the Agent ID
In the Pentium® 4 FSB protocol, whenever a FSB agent initiates a transaction, it must provide its Agent ID in the transaction's Request Phase (i.e., the first phase of the transaction). For this reason, an Agent ID is assigned to each processor on the removal of reset.
Physical versus Logical Processor
In the P6 processor family, there was only one processor within each processor package. In the Pentium® 4 processor family, however, assuming that the Hyper-Threading feature is enabled (see “Hyper-Threading Option” on page 869), each physical processor package contains two logical processors and each of them must be assigned a unique Agent ID on the removal of reset. If Hyper-Threading is disabled, then each physical processor package only contains one processor. It should also be noted that each logical processor within a physical processor package has it own Local APIC that it used to send and receive interrupt messages.
The Agent ID Assignment
Example Xeon MP System with Hyper-Threading Disabled
Figure 36-6 on page 864 shows four Pentium® 4 Xeon MP processors and assumes that Hyper-Threading is disabled. The signal lines BREQ0# through BREQ3# each has a pull-up resistor on the system board (not shown). While the chipset is still asserting reset to the processors, it is a rule that it must drive the BREQ0# signal line low (the chipset is labelled Central Agent in the illustration).
On the removal of reset, all of the processors sample their BR[3:1]# inputs to determine their Agent ID assignments. Remember that due to the pull-up resistors, the BREQ signal lines remain high unless driven low. The truth table in Table 36-1 on page 862 shows the resultant Agent IDs assigned to the four processors.
| BR1# | BR2# | BR3# | Physical Processor ID |
|---|---|---|---|
| 1 | 1 | 1 | 0 |
| 1 | 1 | 0 | 1 |
| 1 | 0 | 1 | 2 |
| 0 | 1 | 1 | 3 |
Example Xeon MP System with Hyper-Threading Enabled
If Hyper- Threading were enabled in the system shown in Figure 36-6 on page 864, each of the physical processors shown has two logical processors within it. The Agent ID assignments would be as shown in Table 36-2 on page 863.
| BR1# | BR2# | BR3# | Physical Processor ID | ID of Logical Processor 0 | ID of Logical Processor 1 |
|---|---|---|---|---|---|
| 1 | 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 0 | 1 | 2 | 3 |
| 1 | 0 | 1 | 2 | 4 | 5 |
| 0 | 1 | 1 | 3 | 6 | 7 |
Dual Processor System with Hyper-Threading Enabled
In a dual-processor system (see Figure 36-7 on page 864), each of the processors only implements the BR0# and BR1# pins (and only BR1# is an input to the processor). The Agent ID assignments are shown in Table 36-3 on page 863.
Figure 36-7. Assignment of Agent ID and Local APIC ID (Dual-Processor System)
| BR1# | Physical Processor | ID of Logical Processor 0 | ID of Logical Processor 0 |
|---|---|---|---|
| 1 | 0 | 0 | 1 |
| 0 | 1 | 2 | 3 |
A Single-Processor System with Hyper-Threading Enabled
In a single processor system, there are two possibilities:
- The processor is a Pentium® 4 (not a Celeron).
- The processor is a Pentium® 4 Celeron.
In either case, the processor only has a BR0# output pin and it “knows” that it's the only processor. Assuming that Hyper-Threading is enabled, the two logical processors are assigned Agent IDs 0 and 1.
The Local APIC ID
The Purpose of the Local APIC ID
As mentioned earlier, each interrupt message transaction contains a destination address that identifies one or more Local APICs that the message is intended for. There are several formats for this destination address and one of them, Physical Destination Mode, specifies the Local APIC ID of the one and only Local APIC that is the recipient of the interrupt message. Another specifies the Cluster ID and Local APIC ID of the target Local APIC. Both necessitate the Local APIC knowing its identity.
The Local APIC ID Assignment
As already described, a logical processor's Agent ID is automatically assigned on the trailing-edge of reset. This same value is also placed in the Local APIC's APIC ID register (see Figure 36-8 on page 865). Software (i.e., the OS) can change the Local APIC ID to another value if it so desires.
While all of Intel®'s current HT-capable processors implement two logical processors, future implementations may implement four or eight logical processors. This would require the Logical Processor field in the APIC ID register to be expanded from one bit to two or three bits. Likewise, although current processors only support up to four physical processor packages on a FSB, this may be expanded to more than four in future implementations, requiring that the Physical Processor field be expanded to more than two bits. In such implementations, the Cluster ID field would be left-shifted as necessary.