Trace Cache Improvements

Increased Trace Cache BTB Size

The Trace Cache BTB size was increased from 512 entries to 2K entries, permitting the processor to maintain execution history on up to 2K conditional branches contained in the Trace cache.

Enhanced Trace Cache μop Encoding

When a complex IA32 instruction is encountered (one that decodes into more than four μops), it is submitted to the Microcode Store ROM which streams the equivalent μops into the pipeline. In addition, a token (consisting of a microcode instruction pointer) representing the complex instruction is placed in the Trace Cache. Whenever it has to be executed, it is sent to the ROM which then streams the resultant μops to the μop Queue.

The 90nm processor's Trace Cache has been improved in that some instructions that had to go to the ROM in the earlier processors can now be stored in the Trace Cache. Two examples are:

• Indirect calls with a register source operand.

• The software PREFETCHh instructions.