Enhanced Power Management Characteristics
Background
For background on the power conservation states available in earlier IA32 processors (including the Pentium® 4), refer to “Pentium® II Power Management Features” on page 683.
Entry to the Deep Sleep State
On the Pentium® 4 and earlier processors, the Deep Sleep state is entered (from the Sleep state) if the chipset causes the system board clock generator to turn off the BCLK to the processor (see Figure 58-1 on page 1431).
Refer to Figure 58-2 on page 1432. The chipset can transition the Pentium® M processor to the Deeper Sleep state (from the Sleep state) by asserting the DPSLP# signal to the processor. Deasserting the DPSLP# signal causes a transition back to the Sleep state.
The processor's PSI# signal remains asserted while the processor remains in the Deep Sleep or the Deeper Sleep state. It is deasserted when the processor exits the Deep Sleep state.
The Deeper Sleep State
On the earlier processors, the lowest power conservation state was the Deep Sleep state. The Pentium® M processor added the Deeper Sleep state (see Figure 58-2 on page 1432).
The Deeper Sleep state is the lowest power state the processor can enter. It is entered when the chipset commands the system board voltage regulator to lower the processor's core operating voltage. With the exception of the lower operating voltage, the Deeper Sleep state is identical to the Deep Sleep State.
Enhanced SpeedStep
Background
Earlier IA32 processors designed for mobile applications implemented the basic form of the SpeedStep technology. Essentially, the processor only had two operating modes:
Lowest Frequency Mode (LFM). While in this mode, the processor operated at lower clock speed and core voltage.
Highest Frequency Mode (HFM). While in this mode, the processor operated at the full clock speed and core voltage.
It should be obvious that having just two operating modes limits the processor's flexibility to match the processor's operating mode to the varying demand loads placed on the processor by the currently-executing application. In addition, the transition time to switch modes was quite lengthy.
Enhanced SpeedStep Description
Rather than just two operational modes, Enhanced SpeedStep implements multiple operational voltage and frequency combinations, ranging from the Lowest Frequency Mode (LFM; LFM speed on all processors is 600MHz) to the Highest Frequency Mode (HFM; the processor is operating at full speed). As an example, Table 58-2 on page 1434 shows the voltage/frequency selections available in the 1.6GHz version of the processor. Please note that the voltage/frequency combinations available are processor design-specific.
| Voltage (Vdc) | Frequency |
|---|---|
| 1.484 | 1.6GHz |
| 1.42 | 1.4GHz |
| 1.276 | 1.2GHz |
| 1.164 | 1GHz |
| 1.036 | 800MHz |
| .956 | 600MHz |
The processor is capable of automatically performing real-time dynamic switching of the voltage and frequency based on CPU demand. This is accomplished by switching the BCLK-to-core clock ratio and the core operating voltage (without resetting the system). In addition, software can control both the operational voltage and frequency. Whether the operational mode is being switched automatically or under software control, the time to transition from operating mode to another is very low.
Voltage/frequency selection is software controlled by writing to MSRs (in earlier designs, the chipset used a draconian approach, manipulating STPCLK#, to cool the processor):
If the target frequency > current frequency, the processor causes the system board voltage regulator to ramp up Vcc by placing a new value on the VID pins and the PLL then locks to the new frequency.
If the target frequency < current frequency, the PLL locks to the new frequency and the Vcc is changed through the VID pin mechanism.
Software transitions are accepted at any time. If a previous transition is in progress, the new transition is delayed until the completion of the previous transition.
The processor controls voltage ramp rates internally to ensure glitch free transitions.
The transition latency is low and a large number of transitions are possible over a short period of time:
The processor's FSB arbiter does not have to be disabled prior to a transition.
No processor cache flush is necessary prior to a transition.
Currently available public domain documentation does not document the MSRs associated with changing the voltage and frequency.