The Previous Chapter
This chapter provided a detailed description of the CPUID instruction. It included:
Prior to the Advent of the CPUID Instruction.
Determining if the CPUID instruction Is Supported.
Determining Basic Request Types Supported.
Determining Extended Request Types Supported.
The Basic Request Types.
Request Type 1.
Request Type 2.
Request Type 3.
Request Type 4.
Request Type 5.
The Extended Request Types.
Enhanced Processor Signature.
This Chapter
This chapter provides a detailed description of System Management Mode (SMM). It includes:
What Falls Under the Heading of System Management?
The Genesis of SMM.
SMM Has Its Own Private Memory Space.
The Basic Elements of SMM.
How the Processor Knows the SM Memory Start Address.
The Organization of SM RAM.
Entering SMM.
Exiting SMM.
The Auto Halt Restart Feature.
The IO Instruction Restart Feature.
Caching from SM Memory.
Setting Up the SMI Handler in SM Memory.
Relocating the SM RAM Base Address.
SMM in an MP System.
The Next Chapter
This chapter provides a complete description of the Local and IO APICs. It includes:
Message Transfer Mechanism Prior to the Pentium® 4.
Message Transfer Mechanism Starting with the Pentium® 4.
A Short History of the APIC.
Detecting the Presence and Version of the Local APIC.
Enabling/Disabling the Local APIC.
Local Cluster and APIC ID Assignment.
Local Interrupt Sources.
Remote Interrupt Sources.
Introduction to Interrupt Priority.
An Intro to Edge-Triggered Interrupts.
An Intro to Level-Sensitive Interrupts.
The Local APIC Register Set.
Locally Generated Interrupts.
Task and Processor Priority.
Interrupt Messages.
The IO APIC.
Message Signaled Interrupts (MSI).
The FSB Message Format.
The APIC Bus Message Format.
The Spurious Interrupt Vector.
The Agents in an Interrupt Message Transaction.
BSP Selection Process.
The APIC, the MPS and ACPI.
3.144.228.78