Before the Advent of the APIC
Most IA32-based systems incorporate an Interrupt Controller that receives interrupt requests from IO devices and passes them to the processor (or, in a multiprocessor system, to one or more of the processors). The Interrupt Controller typically consists of one of the following:
In a single processor PC-AT compatible machine, a pair of cascaded 8259A PICs (Programmable Interrupt Controllers). See Figure 61-1 on page 1500.
In a multiprocessor system, an IO APIC module. See Figure 61-5 on page 1506.
Figure 61-5. The Pentium® 4 Eliminated the APIC Bus
Refer to Figure 61-2 on page 1501. In older chipsets, the Interrupt Controller was incorporated in the PCI-to-ISA Bridge (commonly referred to as the South Bridge), and in the ICH (IO Control Hub) in later chipsets. This was a strategically convenient place for it because the interrupt requests from PCI and ISA devices could easily be connected to it.
Figure 61-2. An External, Hardware Interrupt Delivered to the Processor's INTR Pin
Assuming that the system is a single processor, PC-AT compatible machine (Figure 61-1 on page 1500), the master 8259A asserts its INTR (Interrupt Request) output when it detects any interrupt requests from device adapters. This is connected to the INTR pin (also referred to as the LINT0 pin) on the processor. In response to its assertion, the processor takes the following actions:
Assuming that recognition of external interrupts is enabled (in other words, the programmer has not executed a CLI instruction), the processor will recognize the request when it completes the execution of the current instruction.
The processor temporarily ceases execution of the interrupted program.
The processor generates an Interrupt Acknowledge transaction to obtain the interrupt vector associated with the highest priority request from the Interrupt Controller.
The North Bridge passes the transaction to the PCI bus to make it visible to the chip that contains the Interrupt Controller (i.e., the South Bridge in the example system).
The Interrupt Controller supplies the 8-bit interrupt vector associated with the highest priority request to the North Bridge.
The North Bridge supplies the interrupt vector to the processor.
The processor uses the 8-bit vector as an index into the IDT in memory and reads the CS:EIP value from the selected entry. This CS:EIP value points to the entry point of the interrupt handler within the associated device's driver.
The processor pushes the contents of its CS, EIP and EFlags registers into stack memory (to mark its place in the interrupted program).
The processor then automatically disables recognition of additional external hardware interrupts (i.e., it clears EFlags[IF] to 0).
Using the new CS:EIP value, the processor starts fetching the instructions that comprise the interrupt handler and executes it.
A detailed description of the dual 8259A PICs can be found in chapter 18 of the MindShare book entitled ISA System Architecture, Third Edition.