Interrupt/Exception Priority
It should be fairly obvious that the processor can only execute one program at a time. This being the case, if multiple interrupts and/or exception conditions occurred simultaneously, the processor must decide in what order to service the simultaneous events.
The IA32 processor family divides the possible types of interrupts and exceptions into five classes (listed in Table 14-4 on page 266). Class one is the highest priority group, while class eight is the lowest (the 386 only defined classes 1 through 5). Please note that the table reflects the classes defined as of this writing. The processor services the exception or interrupt from the highest class first. Lower priority exceptions are discarded, while lower priority interrupts are held in the pending state. Discarded exception conditions are generated again when the current handler returns execution to the point of interruption.
| Class | Class Description | Ranking Within Class (highest shown first) |
|---|---|---|
| 1 Highest Priority | Hardware Reset and Machine Checks. | Reset. The platform (i.e., the chipset) asserts the Reset signal to the processor. |
| Machine Check exception due to the detection of a serious hardware-related problem either within the processor on its FSB. | ||
| 2 | Trap on a task switch. | When a switch to a new task occurs, the T bit (Trap bit) is set to one in the TSS of the new task. |
| 3 | Special external hardware interrupts | Flush. The chipset asserts the FLUSH# signal to the processor to force a cache flush (e.g., on a switch to SMM). Starting with the Pentium® 4 processor, the FLUSH# signal is no longer implemented. |
| Stop Clock. The chipset asserts the STPCLK# signal to the processor, commanding the processor to turn off its internal clock (as a power conservation measure). | ||
| SMI. The chipset sends an SMI to the processor to switch the processor into SMM. | ||
| INIT. The chipset sends an INIT to the processor. This is a soft reset [see “Soft Reset (INIT#)” on page 485 for more information]. | ||
| 4 | A Trap on the previous instruction. | Breakpoint caused by the execution of the INT3 breakpoint instruction. |
| Debug trap exceptions due to: | ||
| 5 | External Interrupts. | NMI. The chipset sends a Non-Maskable Interrupt to the processor, typically to report that a serious problem was detected in the platform. |
| A device-related interrupt has been sent to the processor. | ||
| 6 | A Fault caused by the fetch of the next instruction. For the Pentium® and 486, the Code Segment Limit Violation and the Code Page Fault exceptions were assigned to priority class 7. They are in Class 6 on all subsequent processors. | A memory instruction fetch breakpoint address match was detected by the Debug registers. |
| Code segment limit violation. When the EIP value was added to the code segment's base address, the resultant 32-bit linear address exceeded the length of the code segment. | ||
| A Page Fault occurred on an instruction prefetch. | ||
| 7 | A Fault was generated during the decode of the next instruction. | The instruction length is > 15 bytes (includes prefixes). |
| The instruction has an illegal opcode. | ||
| The FPU is not available. This is also referred to as the DNA (Device Not Available) exception. | ||
| 8 Lowest Priority | A Fault was detected during the execution of an instruction. | Overflow. An INTO instruction was executed with EFlags[OF] = 1. |
| A Bound error was detected when the BOUND instruction was executed. | ||
| Invalid TSS. The instruction caused the processor to select a TSS descriptor and the TSS it points to contains invalid information. | ||
| Segment Not Present. An instruction loaded a new value into one of the segment registers. The Segment Present bit in the GDT or LDT descriptor selected = 0, indicating that the segment is not currently present in memory. | ||
| Stack exception. See “Stack Exception (12)” on page 308. | ||
| General Protection. See “General Protection (GP) Exception (13)” on page 310. | ||
| Data Page Fault. The target page on a data access is not currently present in memory. | ||
| Alignment Check. See “Alignment Check Exception (17)” on page 320. | ||
| x87 FPU exception. An error occurred while the x87 FPU was performing a FP operation. | ||
| SIMD FP exception. An error occurred while the processor was executing an SSE or SSE2 FP operation. |