The Write Back Cache
A Line Can Be in One of Four Possible States
At a given moment in time, a line in a WB cache can be in one of four possible states (M, E, S or I):
Invalid (I). This indicates that the selected cache entry is invalid.
Exclusive (E). This indicates three things:
- No other processor currently has a copy of the line.
- The processor's copy of the line is still identical to the one in memory.
- The copy of the line in memory is fresh or clean (i.e., it is up to date).
Shared (S). This indicates three things:
- At least one other processor has a copy of the line. In other words, this processor shares ownership of the line with one or more other processors.
- The copy of the line in the caches of all processors is still identical to the one in memory.
- The copy of the line in memory is fresh or clean (i.e., it is up to date).
Modified (M). This indicates three things:
- One or more bytes within the cached copy of the line have been updated (i.e., written to) since the line was read from memory.
- The line in memory is stale (i.e., it has not received any of the updates that the program running on a processor has made to locations within the line).
- No other processor has a copy of the line in its caches.
Before Storing to a Shared Line, Kill All Other Copies
It is a rule that, if the processor has a Shared copy of a line and the processor experiences a store hit on the line, it cannot store into its copy of the line until it has gained exclusive ownership of the line. In other words, before storing the byte or bytes of write data into the line, the processor must first arbitrate for ownership of the FSB and must issue a Kill transaction specifying the start address of the line to be killed. All of the other processors on the FSB detect the Kill, perform a lookup (a snoop) in their internal caches, and mark their respective copies of the line as Invalid (I). Upon successful completion of the Kill transaction, the processor can then complete the store into its copy of the line and then transition the line from the S state to the M (Modified) state.
On a Store Miss, Perform an RWITM
When a WB cache experiences a store miss, the following actions are taken:
The processor initiates a special form of a memory read transaction on its FSB to fetch the line from memory. On all of the IA32 processors from the Pentium® Pro through the Pentium® 4, this special transaction is known by several names:
If any other processor has a copy of the line in the E or the S state, upon observing the RWITM it invalidates its copy of the line and indicates a cache miss in the snoop result.
If any other processor has a copy of the line in the M state, it indicates this in the snoop result.
The line is sourced to the requester either by the system memory controller or by the snoop agent (i.e., processor) that indicated a hit on a modified copy of the line:
- If there wasn't a hit on a modified copy of the line, the requested line is sourced to the requester by the system memory controller.
- If there was a hit on a modified copy of the line, the requested line is sourced to the requester by the snoop agent (i.e., processor) that indicated a hit on a modified copy of the line. In addition, the snoop agent deletes the line from its cache (i.e., it marks its copy invalid). This is necessary because it knows that the processor that requested the line is going to store into it immediately upon receipt.
When the requesting processor receives the line, it immediately stores into it and marks it Modified (M).
At this point, the line in memory is stale.
If the processor experiences any additional store hits on the M line, it merely updates the line and leaves it in the M state.
Additional Information on the WB Cache
For additional information, refer to “Snooping and the WB Cache” on page 397.