Snooping
General
Whenever any entity attempts to access an area of memory, there must be a mechanism that ensures that the line that it reads from or writes to is a fresh copy of the line—i.e., it cannot be a stale copy of the line that has not received all updates. The entities that could initiate a memory transaction on the processor FSB are:
A processor.
The entity that connects the processor to system memory and to the rest of the system. In an earlier PCI system, this would be the North Bridge or the MCH (Memory Control Hub; see Figure 17-1 on page 395). In a PCI Express system, this would be the Root Complex (see Figure 17-2 on page 396).
The mechanism that ensures this cache consistency is Snooping. Whenever any entity performs a transaction on the processor FSB, the transaction is latched by all FSB agents. If the transaction is any form of a memory transaction, every processor must submit the transaction's memory address to their internal caches for a lookup. This is referred to as a cache Snoop. Each of the processors must then provide a Snoop result to the initiator of the transaction and to the system memory controller in the transaction's Snoop Phase. There are three possible snoop results:
A snoop miss. As you might expect, this indicates that the processor does not have a copy of the line in any of the caches.
A snoop hit on a clean copy of the line. The processor has a copy of the line in at least one of its caches and its copy (or copies) has not been updated and is still the same as the line in memory.
A snoop hit on a modified copy of the line:
- One or more bytes within the cached copy of the line have been updated (i.e., written to) since the line was read from memory.
- The line in memory is stale (i.e., it has not received any of the updates that the program running on a processor has made to locations within the line).
- No other processor has a copy of the line in its caches.
On IA32 processors from the Pentium® Pro through the Pentium® 4 product line, the snoop result is provided on two signals: HIT# and HITM# (the pound sign after the signal name means that the signal is asserted when it is driven to the electrically low state).
Snooping and the WT Cache
Introduction
When a memory transaction is initiated on the processor FSB, any processor on the FSB must snoop the transaction in its cache. The effect that the snoop has on the request initiator, the snooping processors and on system memory depends on whether the transaction is a memory read or write. This discussion assumes that the snooping processors have a WT cache. Remember that an entry in a WT cache can only be in one of two possible states—Invalid (I) or Shared (S):
Snooping a Memory Read in a WT Cache
There are two possible cases:
If the line being snooped is in the I state, the snooping processor indicates a snoop miss to the request initiator and to the system memory controller. The line is sourced to the requester from system memory and the requester puts the line in its cache in the S state (indicating that the line is valid).
If the line being snooped is in the S state, the snooping processor leaves its copy of the line in the Shared (S) state and indicates a hit on a clean line to the request initiator and to the system memory controller. The line is sourced to the requester from system memory and the requester puts the line in its cache in the S state (indicating that the line is valid).
Snooping a Memory Write in a WT Cache
There are two possible cases:
If the line being snooped is in the I state, the snooping processor indicates a snoop miss to the request initiator and to the system memory controller. The data is written into the line in system memory.
If the line being snooped is in the S state, the snooping processor kills its copy of the line and indicates a snoop miss to the request initiator and to the system memory controller. The data is written into the line in system memory. The snooping processor has to kill its copy because IA32 processor cannot snarf (i.e., latch) data that is being written to memory by another entity.
Snooping and the WB Cache
Introduction
When a memory transaction is initiated on the processor FSB, any processor on the FSB must snoop the transaction in its cache. The effect that the snoop has on the request initiator, the snooping processor and system memory depends on whether the transaction is a memory read or write. This discussion assumes that the snooping processor(s) has a WB cache. Remember that an entry in a WB cache can be one of four possible states—M, E, S or I (see “A Line Can Be in One of Four Possible States” on page 391).
Snooping a Memory Read in a WB Cache
There are four possible cases:
If the snoop results in a miss, the snooping processor indicates this to the requester and to the system memory controller in the transaction's Snoop Phase and the line is sourced to the requester from system memory. Assuming that it was a miss in the caches of all of the snooping processors, the requesting processor places the line in its cache in the E state.
If the snoop results in a hit on a copy of the line in the E state, the snooping processor indicates (in the transaction's Snoop Phase) that it's a hit on a clean copy of the line to the requester and to the system memory controller and the line is sourced to the requester from system memory. The snooping processor transitions the state of its line from E to S. The requesting processor places the line in its cache in the S state.
If the snoop results in a hit on a copy of the line in the S state, the snooping processor indicates (in the transaction's Snoop Phase) that it's hit on a clean copy of the line to the requester and to the system memory controller and the line is sourced to the requester from system memory. The snooping processor leaves its copy of the line in the S state. The requesting processor places the line in its cache in the S state.
If the snoop results in a hit on a copy of the line in the M state, the snooping processor indicates (in the transaction's Snoop Phase) this to the requester and to the system memory controller. As a result, the system memory controller cancels the read from memory. In the memory read transaction's Data Phase, the snooping processor sources the modified line to the requester and to the system memory controller. The memory controller latches the line and uses it to update its stale copy in memory. The requester places the line in its cache in the S state. The snooping processor transitions the state of its copy of the line from M to S.
Snooping a Memory Write in a WB Cache
There are four possible cases:
If the snoop results in a miss, the snooping processor indicates this to the requester and to the system memory controller in the transaction's Snoop Phase. The line in system memory is updated by the write.
If the snoop results in a hit on a copy of the line in the E state, the snooping processor kills its copy of the line and indicates (in the transaction's Snoop Phase) that it's a miss to the requester and to the system memory controller. The line in system memory is updated by the write.
If the snoop results in a hit on a copy of the line in the S state, the snooping processor kills its copy of the line and indicates (in the transaction's Snoop Phase) that it's a miss to the requester and to the system memory controller. The line in system memory is updated by the write.
If the snoop results in a hit on a copy of the line in the M state, the snooping processor indicates (in the transaction's Snoop Phase) this to the requester and to the system memory controller. The following actions occur:
- The snooping processor unloads the modified line from its cache (so its copy is now in the I state) and places it in a writeback buffer within its FSB interface unit.
- The system memory controller first accepts the memory write data from the entity that initiated the write (typically, this would be the North Bridge, MCH, or Root Complex) and the write data is placed in a buffer in the memory controller.
- The memory controller signals to the snooping processor and that processor sources the modified line to the memory controller. The line is placed in a second buffer in the controller.
- The memory controller then merges the write data from the first buffer into the appropriate byte locations within the second buffer (that contains the modified line) and then writes the updated line from the second buffer into memory.