How the APs are Discovered and Configured
The Intel® MultiProcessing (MP) 1.4 specification (available for download at the Intel® developers' web site) states that the startup code executed by the BSP is responsible for detecting the presence of processors other than the BSP. As part of this process, two tables are created: the MP Table and the ACPI table. When an MP-aware OS is booted, the OS consults one or the other of these tables to discover how many and what type of processors it has to work with.
AP Detection and Configuration
According to the Multiprocessor Specification, the BIOS/POST code is responsible for detecting the presence of and initializing the APs. Intel® recommends that this be accomplished as shown in the flowchart in Figure 37-5 on page 891 and Figure 37-6 on page 892. The flowchart assumes that Hyper-Threading is enabled in each of the processors.
Figure 37-5. BIOS's AP Discovery Procedure Part 1
Figure 37-6. BIOS's AP Discovery Procedure Part 2
Introduction
A startup message (i.e., a SIPI—Startup Inter-Processor Interrupt message) will be broadcast to all of the APs (assuming any are present). The vector field in this message selects an entry in the Interrupt Table that points to the FindAnd InitAllCPUs routine. Upon receipt of this message, all of the APs simultaneously request ownership of the Request Phase signal group to begin fetching and executing the FindAndInitAllCPUs routine. To prevent all of the processors from simultaneously executing the body of this routine, a semaphore is tested upon entry into the routine to determine if the body of the routine may be executed. The first AP processor that is successful in testing and setting the semaphore can execute the body of the routine, while the other APs go into a program spin loop waiting for the winning processor to clear the semaphore. In this way, each of the processors in succession gets to execute the body of the routine.
The BIOS's AP Discovery Procedure
The following is a slightly expanded version of the flowchart. The BIOS code executing on the BSP:
1. | If necessary, loads a microcode update into the BSP (see “MicroCode Update Feature” on page 631 for a detailed description). |
2. | Initializes the MTRRs and defines the 4KB address range assigned to the logical processor's Local APIC register set as UC memory. |
3. | Enables caching by clearing the CR0[CD] and CR0[WT] bits to zero. |
4. | Executes a CPUID request type 0 to determine if the BSP is “GenuineIntel.” |
5. | Executes a CPUID request type 1 and saves the information returned in the EAX, EBX and EDX registers in system configuration RAM for use later. |
6. | Loads the AP start-up code (the Intel® MP spec refers to it as the FindAnd InitAllCPUs routine) into the first MB of memory on a 4KB-aligned page boundary. |
7. | Switches the BSP into Protected Mode. This is necessary because some of the steps that follow necessitate accessing the Local APIC's register set (which is in high memory and cannot be accessed in Real Mode). |
8. | Reads the BSP's Local APIC ID from its Local APIC ID register and saves it in the ACPI and MP tables and optionally in system configuration RAM. |
9. | Converts the 4KB-aligned base address of the AP startup program into an 8-bit vector (e.g., a vector of BDh specifies a start-up memory address of 000BD000h). |
10. | Enables the Local APIC by setting Spurious Vector Register (SVR; see Figure 37-7 on page 893) bit 8 = 1. Figure 37-7. The Local APIC's Spurious Vector Register
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11. | Sets up the Local APIC's LVT (Local Vector Table) Error register. It sets the register's vector field = a vector that selects an IDT entry which points to the error handler for the Local APIC. See “The Local Vector Table” on page 1539. |
12. | Clears the memory semaphore that each AP will check in order to gain entry to the AP start-up program. |
13. | Sets a CPU count variable in RAM = 1, indicating the current count of known processors (so far, only the BSP is known to exist). |
14. | Commands its Local APIC to broadcast a SIPI (Startup IPI) message to all Local APICs within all physical processors (including itself). This SIPI contains the vector that represents the 4KB-aligned start address of the AP start-up program. |
15. | Start a 100ms timer (using the Local APIC's integrated timer). This is more than enough time for all of the logical processors that may be present in the system to have completed execution of the AP startup program. |
16. | When the 100ms timer has expired an interrupt is generated and the BIOS checks the CPU counter location in RAM to see if it still contains the value 1. If it doesn't, then the counter was incremented by one or more APs in the system. If it still = 1, then there are no APs. |
When the BSP has completed execution of the POST/BIOS code and has configured and enabled the devices necessary to read the OS startup code from a mass storage device, it executes the OS boot to begin the process of reading the OS startup code into memory and, after doing so, passes control to the OS startup code.
The OS startup code is responsible for reading the remainder of the OS kernel into memory. Assuming that the OS is MP-aware, it consults either the MP table or the ACPI table to determine how many and what type of processors it has to work with.
Uni-Processor OS
If the OS (e.g., DOS) is not capable of recognizing the existence of the APs, they remain dormant and are never used (in other words, they suck power and are a waste of money).
MP OS
If the OS is a Multi-Processing (MP) OS, it must:
Consult the MP table built in CMOS memory to determine the presence (or absence) of the other processors (the APs).
Place tasks in memory for them to execute.
Using a startup message, pass the start address of these programs to each of them.
The FindAndInitAllCPUs Routine
Upon receipt of the startup message issued by the BSP's Local APIC under the control of the BIOS code, each of the APs simultaneously begin to fetch and execute the FindAndInitAllCPUs routine. This routine performs the functions shown in the flowchart in Figure 37-8 on page 895 and Figure 37-9 on page 896.
The first AP that executes the semaphore test at the start of the FindAnd InitAllCPUs routine determines that the semaphore is clear (the BIOS code cleared it to 00h before issuance of the startup message). It sets the semaphore to FFh, thereby indicating that it and no other AP will execute the body of the FindAndInitAllCPUs routine until it completes its execution and clears the semaphore. The following is an example of the semaphore test and set operation (note that an IA32 processor automatically asserts its LOCK# output when performing the memory read and write transactions associated with an exchange instruction):
mov al,FFh TestLock: xchg byte ptr [Semaphore],al ;read and set semaphore cmp al,FFh ;test value read jz TestLock ;spin if already set ;execute body of FindAndInitAllCPUs routine (see next step)When each of the remaining logical processors reads the semaphore, it has already been set by the winner, so each of them enters a spin loop waiting for the semaphore to be cleared. The winning logical AP executes the body of the routine which accomplished the tasks in the steps that follow.
If necessary, the routine loads a microcode update into the processor.
It initializes the MTRRs with the same settings as in the BSP.
It enables the caches by clearing the CR0[CD] and CR0[WT] bits to zero.
It executes a CPUID request type 0 to determine if the AP is “GenuineIntel”.
It executes a CPUID request type 1 and saves the information returned in the EAX, EBX and EDX registers in configuration RAM.
It switches to the AP into Protected Mode. This is necessary because some of the steps that follow necessitate accessing the Local APIC's register set (which is in high memory and cannot be accessed in Real Mode).
It reads the AP's Local APIC ID from its Local APIC ID register, and adds it to the MP and ACPI tables and optionally to the system configuration info in RAM.
It enables the Local APIC by setting Spurious Vector Register (SVR; see Figure 37-7 on page 893) bit 8 = 1.
It sets up the Local APIC's LVT (Local Vector Table) Error register. It sets the register's vector field = a vector that selects an IDT entry which points to the error handler for the Local APIC. See “The Local Vector Table” on page 1539.
It configures the AP's SMI execution environment (each AP and the BSP must have a different SM Base address). See “System Management Mode (SMM)” on page 1463 for more information.
It increments the CPU counter variable by 1.
It clears the semaphore, thereby permitting the other APs to execute the body of the AP start-up program. The following is an example of the semaphore clear operation:
ReleaseLock: mov al,00h xchg byte ptr[Semaphore],al ;clear semaphore to 00h ;go to next stepIt executes a CLI instruction to disable recognition of external hardware interrupts, and a HLT instruction to place the AP in low-power mode while it awaits the pleasure of the MP OS's commands.
It awaits the receipt of an INIT IPI. This will be sent later by the MP OS (after it has been booted).
Figure 37-8. AP Setup Program Part 1
Figure 37-9. AP Setup Program Part 2
