Introduction to Interrupt Priority
General
Table 61-1 on page 1518 is a subset of Table 14-4 on page 267 and shows the priority relationship of the various types of interrupts to each other in the event that multiple interrupt types are received by the Local APIC simultaneously. As an example, if the processor were to simultaneously receive an SMI and an NMI interrupt, the SMI would be serviced first followed by the NMI (when the processor has completed servicing the SMI).
| Class | Class Description | Ranking Within Class (highest shown first) | Handled by APIC? |
|---|---|---|---|
| 3 Highest Priority | Special external hardware interrupts | Flush. The chipset asserts the FLUSH# signal to the processor to force a cache flush (e.g., on a switch to SMM). Starting with the Pentium® 4 processor, the FLUSH# signal is no longer implemented. | No |
Stop Clock. The chipset asserts the STPCLK# signal to the processor, commanding the processor to turn off its internal clock (as a power conservation measure). | No | ||
SMI. The chipset sends an SMI to the processor to switch the processor into SMM. | Yes | ||
INIT. The chipset sends an INIT to the processor. This is a soft reset [see “Soft Reset (INIT#)” on page 485 for more information]. | Yes | ||
| 5 | External Interrupts. | NMI. The chipset sends a Non-Maskable Interrupt to the processor, typically to report that a serious problem was detected in the platform. | Yes |
| An interrupt message containing a vector value between 32 and 255 decimal. | Yes |
Definition of a User-Defined Interrupt
Interrupt vector values 0 through 31 (decimal) are reserved for IA32 architecturally-defined interrupts and exceptions (see Table 14-3 on page 261). As noted in Table 14-1 on page 256, in a PC-compatible machine the interrupt vector values in the 8 through 15 range are shared by software exception types and hardware interrupts.
A user-defined interrupt is one that is not generated by the processor (it is delivered by the system board logic or by the OS to the processor's Local APIC) and that has an interrupt vector value in the 32 to 255 (decimal) range.
When an interrupt message containing a vector in the range of 0 through 15 (decimal) is sent or received through the Local APIC, the Local APIC sets the Received Illegal Vector or Send Illegal Vector bit in its Error Status Register (see Figure 61-14 on page 1519). Note that although the vectors 16 through 31 (decimal) are reserved for processor exceptions, the Local APIC will not generate an error on the send or receive of an interrupt message using one of these vectors.
The Priority Amongst the User-Defined Interrupts
Consider a scenario wherein none of the higher-priority interrupts (SMI, INIT or NMI) are pending and the Local APIC receives multiple interrupt messages containing user-defined interrupt vectors (in the 32 to 255 range). In what order does the Local APIC dispatch these interrupts to the processor core (in other words, what is the priority scheme)?
Refer to Table 61-2 on page 1520. The 256 possible interrupt vectors are divided into 16 groups, or classes, of 16 interrupt vectors each. Vectors within interrupt priority class 15 (vectors 241 through 255) have the highest priority, while those within interrupt priority class 1 (vectors 16 through 31) have the lowest priority. Interrupt priority class 0 is not included because those 16 vectors (0 to 15) are dedicated for processor exceptions (see Table 14-4 on page 267). Although the Local APIC can send or receive an interrupt message with a vector in the 16 to 31 range (interrupt class 1) without generating an error, this would be ill-advised as those 16 vectors, like those in class 0, are also dedicated for processor exceptions (see Table 14-4 on page 267). Priority classes 0 and 1 are shaded in the table because they are not user-defined interrupt vectors.
| Interrupt Class | Vector Number | Priority |
|---|---|---|
| 0. This class 0 is not included because those 16 vectors are dedicated for processor exceptions (see Table 14-4 on page 267) | 0 - 15 | |
| 1. Although an interrupt message could be sent or received with a vector in the 16 to 31 range without causing the Local APIC to generate an error, this would be ill-advised because those 16 vectors are also dedicated for processor exceptions (see Table 14-4 on page 267). | 16 - 31 | Within this class, 16 is the lowest and 31 is the highest priority.
Note: Technically-speaking, this is the lowest-priority user-defined priority class, but as noted in the left column, these 16 vectors should not be used as user-defined interrupts. |
| 2 is the lowest user-defined priority class and 15 is the highest. | 32 - 47 | Within this class, 32 is the lowest and 47 is the highest priority. |
| 3 | 48 - 63 | Within this class, 48 is the lowest and 63 is the highest priority. |
| 4 | 64 - 79 | Within this class, 64 is the lowest and 79 is the highest priority. |
| 5 | 80 - 95 | Within this class, 80 is the lowest and 95 is the highest priority. |
| 6 | 96 - 111 | Within this class, 96 is the lowest and 111 is the highest priority. |
| 7 | 112 - 127 | Within this class, 112 is the lowest and 127 is the highest priority. |
| 8 | 128 - 143 | Within this class, 128 is the lowest and 143 is the highest priority. |
| 9 | 144 - 159 | Within this class, 144 is the lowest and 159 is the highest priority. |
| 10 | 160 - 175 | Within this class, 160 is the lowest and 175 is the highest priority. |
| 11 | 176 - 191 | Within this class, 176 is the lowest and 191 is the highest priority. |
| 12 | 192 - 207 | Within this class, 192 is the lowest and 207 is the highest priority. |
| 13 | 208 - 223 | Within this class, 208 is the lowest and 223 is the highest priority. |
| 14 | 224 - 239 | Within this class, 224 is the lowest and 239 is the highest priority. |
| 15 is the highest priority class and 0 is the lowest. | 240 - 255 | Within this class, 240 is the lowest and 255 is the highest priority. |
Within each group of 16 user-defined vectors, the lowest numbered vector has the lowest priority while the highest numbered one has the highest priority.
Definition of Fixed Interrupts
The user-defined interrupts are frequently referred to as fixed interrupts in the APIC documentation. When an interrupt message is received and it specifies the Fixed Delivery Mode, this instructs the Local APIC to use the 8-bit vector that was delivered in the message and to prioritize the interrupt as a user-defined interrupt (see “The Priority Amongst the User-Defined Interrupts” on page 1519).
When an interrupt message is received that specifies the NMI, SMI, INIT, ExtINT, SIPI, or INIT-deassert Delivery Mode, the Local APIC ignores the 8-bit vector that was delivered in the message.
Masking User-Defined Interrupts
While each of the interrupts associated with the LVT has its own Mask bit, the user-defined interrupts cannot be individually masked. Rather, executing the CLI instruction mass disables recognition of all of the user-define interrupts, while executing the STI instruction mass enables recognition of all of them.