The Previous Chapter
This chapter provided a detailed description of how the processor handles automatic task switching. It also covered Linked Tasks, Linkage Modification, the Busy Bit, and address mapping issues.
This Chapter
This chapter provides a complete description of 386-style demand mode paging. This discussion is also directly applicable to all subsequent IA processors. Table 12-5 on page 244 provides linkage to all of the paging-related enhancements that appeared in subsequent IA32 processors.
Processor | Enhancement | Described in |
---|---|---|
486 | Write Protect feature | A complete description can be found in “The Write Protect Feature” on page 450. |
Caching Rules | A complete description can be found in “Directory/Table and Page Caching” on page 451. | |
Pentium® | 4MB Pages | A complete description can be found in “4MB Pages” on page 501. |
Global pages | A complete description can be found in “Global Pages” on page 567. | |
Pentium® Pro | PAE-36 Mode | A complete description can be found in “PAE-36 Mode” on page 554. |
Pentium® II | PSE-36 Mode | A complete description can be found in “PSE-36 Mode” on page 731. |
PAT feature | A complete description can be found in “PAT Feature (Page Attribute Table)” on page 797. |
The Next Chapter
This chapter describes how usage of the Flat Model can effectively eliminate segmentation from the picture. It should be noted that virtually all modern OSs utilize the Flat Model.
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